Miodrag Milanovic
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db5d26c129
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Validate DSPs
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2024-11-26 10:58:38 +01:00 |
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Miodrag Milanovic
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1e08d7b931
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wip
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2024-11-26 10:58:38 +01:00 |
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Miodrag Milanovic
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243384d31c
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wip
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2024-11-26 10:58:38 +01:00 |
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Miodrag Milanovic
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dddfcec4b9
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wip
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2024-11-26 10:58:38 +01:00 |
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Miodrag Milanovic
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d14efa1c9b
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Pack and export DSP
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2024-11-26 10:58:38 +01:00 |
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Miodrag Milanovic
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d3d3b56b25
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Place at LOC
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2024-11-26 10:58:38 +01:00 |
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Miodrag Milanovic
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c2ce766503
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Constraing to location if provided
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2024-11-26 10:58:38 +01:00 |
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Miodrag Milanovic
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5d5be7df63
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Cover more global routing cases
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2024-11-26 10:58:38 +01:00 |
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Miodrag Milanovic
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ca2751277d
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pack and export GCK, WFG and PLL
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2024-11-26 10:58:38 +01:00 |
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Miodrag Milanovic
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bb34a6fa8f
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Fix CY packing
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2024-11-26 10:58:38 +01:00 |
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Miodrag Milanovic
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d9b437d705
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Use ctx->idf where applicable
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2024-11-26 10:58:38 +01:00 |
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Miodrag Milanovic
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c493c989f0
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Validations and fixes for RAM I/Os
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2024-11-26 10:58:38 +01:00 |
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Miodrag Milanovic
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04653621e8
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Add structure for clock sinks
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2024-11-26 10:58:38 +01:00 |
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Miodrag Milanovic
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13e323d2cf
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Proper port used only on RFB
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2024-11-26 10:58:38 +01:00 |
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Miodrag Milanovic
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ba805f67be
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Better RF/XRF handling
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2024-11-26 10:58:38 +01:00 |
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Miodrag Milanovic
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1437f1c209
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Initial memory support
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2024-11-26 10:58:38 +01:00 |
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Miodrag Milanovic
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3dedb11434
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Add IOM insertion
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2024-11-26 10:58:38 +01:00 |
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Miodrag Milanovic
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0a4cfb77db
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Implementation as in D2 deliverable
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2024-11-26 10:57:30 +01:00 |
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