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Commit Graph

576 Commits

Author SHA1 Message Date
David Shah
7123209324 Allow selection of router algorithm 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:54:38 +00:00
David Shah
ad1cc12df1 router2: Make magic numbers configurable 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:38:31 +00:00
David Shah
5e1aac67db ecp5: Improve bounding box accuracy 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:38:31 +00:00
David Shah
d2c77fd9ae ecp5: router2 main rename 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:38:31 +00:00
David Shah
abdaa9c8a1 ecp5: Router2 test integration 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:38:30 +00:00
Erika
9185c85a54 python: Expose PlaceStrength enum and isValidBelForCell on ecp5 
Signed-off-by: Erika <rrika9@yahoo.com>
 2020-01-26 20:32:02 +00:00
David Shah
3b5e64e8c6 ecp5: Fix tieoff of unused DELAY signals 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-21 19:02:26 +00:00
David Shah
7c81d4e630 ecp5: Add SPICB0 IO support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-20 20:30:14 +00:00
David Shah
9dc8e1e35d ecp5: Don't reroute existing globals 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-20 14:58:38 +00:00
Miodrag Milanovic
714769e1b8 Few more caught by clang 2020-01-18 15:58:09 +01:00
David Shah
54c1bc1538
Merge pull request #382 from YosysHQ/ecp5-psuedodiff 
ecp5: Add support for top pseudo diff outputs
 2020-01-16 09:38:00 +00:00
David Shah
f513d5fff4 ecp5: Add support for top pseudo diff outputs 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-15 11:43:12 +00:00
Larry Doolittle
eba6ea53f8 More adjustments to .bba file locations 
Follows PM discussion with Marcus Comstedt.
Extend changes in .bba file location (made in commit b6a7b60) to ice40 and MSVC cases,
  so all cases become compatible with read-only access to git tree.
Only known down-side is inefficiency when building out-of-tree for multiple architectures;
  people following that use case should consider using PREGENERATED_BBA_PATH.
It would be nice if there were less copy-paste in MSVC vs. non-MSVC content in family.cmake,
  but that would have to be addressed by someone more skilled in Cmake and MSVC.
 2020-01-14 12:28:40 -08:00
Larry Doolittle
b6a7b607fd Remove barrier to out-of-tree builds 
With this change, nextpnr can build successfully (and run correctly) using the git tree as a read-only reference.
No change in behavior observed for in-tree builds.
 2020-01-12 21:11:56 -08:00
Miodrag Milanovic
fb5480cde3 clangformat 2019-12-28 15:02:13 +01:00
Miodrag Milanovic
59f4755e8f made most of frequent numbers constants 2019-12-28 15:01:36 +01:00
Miodrag Milanovic
6cca93543b move constants to gfx.cc 2019-12-28 14:27:14 +01:00
Miodrag Milanovic
6ebe2fd034 remove synt example 2019-12-28 14:08:58 +01:00
Miodrag Milanovic
796d648995 Merge remote-tracking branch 'origin/master' into mmicko/ecp5_gui 2019-12-28 13:54:06 +01:00
Miodrag Milanovic
50f87a6024 add newline at eof 2019-12-28 13:51:02 +01:00
David Shah
0d43aff268 ecp5: Always promote IOLOGIC SCLK to global 
Fixes #374

Signed-off-by: David Shah <dave@ds0.me>
 2019-12-27 15:53:00 +00:00
David Shah
fe40094216 Preserve hierarchy through packing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-27 10:44:30 +00:00
David Shah
b100087024 python: Add bindings for hierarchy structures 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-27 10:44:30 +00:00
David Shah
b6e2159cec Work around Qt MOC issue with IdString enums 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-27 10:32:23 +00:00
Miodrag Milanovic
a05954249a optimize and set order 2019-12-20 14:02:00 +01:00
Miodrag Milanovic
c26c5e7b8e clang format 2019-12-20 09:07:03 +01:00
Miodrag Milanovic
e4210e7fd3 Add all missing wires 2019-12-20 09:05:58 +01:00
Miodrag Milanovic
b271e59472 Add global wires 2019-12-15 17:20:48 +01:00
Miodrag Milanovic
d5174110fa more pips on connection box 2019-12-15 10:57:24 +01:00
Miodrag Milanovic
f2b8e347a9 cleanup and formating 2019-12-15 10:43:30 +01:00
Miodrag Milanovic
2872b500e3 make it more simetric 2019-12-15 10:33:12 +01:00
Miodrag Milanovic
bbc05f3113 optimize and add some missing pips 2019-12-15 10:07:55 +01:00
Miodrag Milanovic
3d42097e9d cleanup 2019-12-15 09:45:09 +01:00
Miodrag Milanovic
fa55a826b2 cleanup wire 2019-12-15 09:26:25 +01:00
Miodrag Milanovic
436260e47e move bel creation to gfx.cc 2019-12-15 09:21:58 +01:00
Miodrag Milanovic
fb27f1a031 fix formating 2019-12-14 16:40:27 +01:00
Miodrag Milanovic
cce27e72f0 lot more pips 2019-12-14 16:29:25 +01:00
Miodrag Milanovic
abf9bc3bb9 fixes and more pips 2019-12-14 16:10:41 +01:00
Miodrag Milanovic
d42ecc081e pips for alu, mult and memory 2019-12-14 13:00:09 +01:00
Miodrag Milanovic
7e7e20742d pips for ios 2019-12-14 12:30:04 +01:00
Miodrag Milanovic
601360b73a propagate w and h 2019-12-14 10:56:26 +01:00
Miodrag Milanovic
e118e418e5 pips for other type of connection box 2019-12-14 09:39:41 +01:00
Miodrag Milanovic
ebbfb6375d more new wires added 2019-12-14 09:18:24 +01:00
Miodrag Milanovic
19eb16045f ebr, mult and alu nice display 2019-12-14 08:21:02 +01:00
Miodrag Milanovic
6d005f38b5 add more 2019-12-13 19:44:49 +01:00
Miodrag Milanovic
2a5f0bbd28 new wires in db 2019-12-13 18:24:49 +01:00
Miodrag Milanovic
c0585e98eb added siologic 2019-12-13 14:32:27 +01:00
Miodrag Milanovic
16f6aaa68c Add many new wires 2019-12-13 14:01:28 +01:00
Miodrag Milanovic
7fd856b866 clangformat run 2019-12-08 09:33:06 +01:00
Miodrag Milanovic
275805d78f display IOs properly 2019-12-07 19:06:10 +01:00
Miodrag Milanovic
401bee6111 More bels show properly 2019-12-07 18:52:33 +01:00
Miodrag Milanovic
76d2a3f0db add dcca bels and dummy parts for other bels 2019-12-07 17:41:22 +01:00
Miodrag Milanovic
b764f9b13a Fix edge wires 2019-12-07 17:21:59 +01:00
David Shah
349be76d26 ecp5: Add support for flipflops with preload 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-07 12:20:25 +00:00
Miodrag Milanovic
0c77eed07d add more pips 2019-12-01 11:00:24 +01:00
David Shah
1c1c096861 ecp5: Fix 25k DDRDLLA bitstream gen 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-29 10:56:04 +00:00
David Shah
ff30bc87fe ecp5: Fix placement of DDRDLLA 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-29 10:50:13 +00:00
David Shah
b4e9f5c3a6
Merge pull request #356 from YosysHQ/ecp5-ff-density 
ecp5: Improve flipflop packing density
 2019-11-27 11:22:14 +00:00
David Shah
98fe4438f1 ECP5 support is no longer experimental 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-26 16:10:53 +00:00
David Shah
aee2e01983 ecp5: Improve flipflop packing density 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-20 18:22:22 +00:00
David Shah
08cf545d9b Revert "Merge pull request #355 from YosysHQ/ecp5-promote-lsr" 
This reverts commit 6a7d1fe53d, reversing
changes made to c3d4117a21.
 2019-11-20 17:10:11 +00:00
David Shah
67e216f8fb ecp5: Add support for promotion of LSRs to global network 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-19 14:08:35 +00:00
David Shah
c3d4117a21 ecp5: Fix handling of custom DEL_VALUE 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-18 22:03:11 +00:00
David Shah
36c0ff2dbc ecp5: Fix dynamic DELAYF control 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-18 20:58:08 +00:00
David Shah
9a848d9d76 ecp5: Add logic utilisation before packing statistics 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-18 16:54:42 +00:00
David Shah
d08e2ade88
Merge pull request #345 from YosysHQ/dave/sdf 
Improve handling of top level IO and add SDF support
 2019-11-18 14:28:40 +00:00
Miodrag Milanovic
da8b5758cd Handle H00 and V00 2019-11-11 13:30:11 +01:00
Miodrag Milanovic
2827731210 More pips and fix for V01 2019-11-11 12:49:26 +01:00
Miodrag Milanovic
522bbbc1f2 cleanup 2019-11-11 09:32:28 +01:00
Miodrag Milanovic
6e349db55b proper h06 and v06 2019-11-11 08:58:46 +01:00
Miodrag Milanovic
afea345cc7 More pips added 2019-11-10 17:02:18 +01:00
Miodrag Milanovic
74f2c4a73b more pips, and valid mapping 2019-11-10 15:24:06 +01:00
Miodrag Milanovic
43c7b4fa21 Fixed V2, some more pips 2019-11-10 11:10:13 +01:00
Miodrag Milanovic
9a9265f4d2 more pips 2019-11-10 10:08:02 +01:00
Miodrag Milanovic
f6d74cb7a9 Draw some pips, fixed H6 and V6 2019-11-09 13:12:20 +01:00
David Shah
21c09c8b8f ecp5: Copy timing constraints across ECLKBRIDGECS 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-01 16:27:51 +00:00
David Shah
58b7cb920f ecp5: Fix placement of ECLKBRIDGECS 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-01 16:07:51 +00:00
David Shah
5cf0ed5ede ecp5: Allow setting drive strength for 3V3 IOs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-26 22:21:18 +01:00
David Shah
bac8335222 ecp5: Add constids for new timing cell types 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-26 20:50:50 +01:00
David Shah
475fcd4425 ecp5: Add an error for out-of-sync constids and bba 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-26 20:38:28 +01:00
David Shah
36c07a0f45 ecp5: Fix routing to shared DSP control inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-25 09:37:13 +01:00
Miodrag Milanovic
49760a9ea8 Show V02/V06/H02/H06 2019-10-25 09:28:08 +02:00
Miodrag Milanovic
d1feb2aa2d display horizontal wires, add some globals to list 2019-10-23 18:17:08 +02:00
David Shah
b582ba810c ecp5: Make database build depend on constids.inc 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-20 10:29:07 +01:00
Miodrag Milanovic
0d2ae5cc9d Split graphics calls for wires into gfx.cc 2019-10-20 11:12:26 +02:00
Miodrag Milanovic
847910d986 type needs to be part of hash for GroupId 2019-10-20 10:03:37 +02:00
Miodrag Milanovic
e9ae0cf7ce muxes only together with slices 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
eaf760768b Remove not used line 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
e69bb4c077 Simplify layout of elements 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
3b01d2fbce fix slice wire 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
399a137a77 bound signals 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
8c79044d43 more wires between switchboxes 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
4cbdc388b8 Add more types of wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
28d0313ccc Less types needed 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
966d0dec19 finixed slice wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
74da9cc424 wd wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
4b79050ef4 Fix look of some wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
a59faa8df0 Add output wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
07a8022a1f fix mux display 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
a11cc8791b set wire active flag 2019-10-20 09:41:48 +02:00