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Author SHA1 Message Date
gatecat
dcb09ec8de interchange: Implement getWireType 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-30 11:07:31 +01:00
gatecat
ecf24201ec interchange: Add wire types to chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-30 11:07:14 +01:00
gatecat
d718ccaa78
Merge pull request #689 from adamgreig/ecp5-alu 
ECP5 ALU54B placement support
 2021-04-29 10:50:28 +01:00
Adam Greig
d3a6cf3ae7
Only set CIBOUT_BYP on MULTs that are not feeding an ALU. 2021-04-29 02:23:45 +01:00
Adam Greig
b6c608e038
Add check_alu to Ecp5Packer 
Checks that every ALU54B is correctly connected to two MULT18X18Ds:

* SIGNEDIA and SIGNEDIB connected to SIGNEDP
* MA and MB connected to P
* A and B connected to {ROA, ROB}

Diamond enforces these requirements; the connections are fixed
in any event so no other connection is possible.
 2021-04-29 02:23:44 +01:00
Adam Greig
d4c688297c
Add relative constraints to position MULT18X18D near connected ALU54B. 2021-04-29 02:23:43 +01:00
Adam Greig
9538954cc6
Add ALU54B.REG_OPCODEOP1_1_CLK parameter support 2021-04-29 02:23:42 +01:00
gatecat
b7bf7c11a8
Merge pull request #685 from YosysHQ/gatecat/nexus-routing 
nexus: Enable placeAllAtOnce
 2021-04-25 12:46:14 +01:00
gatecat
0abe425675 nexus: Enable placeAllAtOnce 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-25 11:53:21 +01:00
gatecat
3fd1ee7757
Merge pull request #683 from antmicro/interchange-allow-loc-keyword 
interchange: allow LOC keyword in XDC files
 2021-04-20 14:12:14 +01:00
Jan Kowalewski
d1548ed317 interchange: allow LOC keyword in XDC files 
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
 2021-04-20 14:35:15 +02:00
gatecat
95698827b8
Merge pull request #682 from YosysHQ/gatecat/default-cellpins 
interchange: Handle missing/disconnected cell pins
 2021-04-20 11:33:51 +01:00
gatecat
0e6955a08d interchange: Bump versions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-20 10:42:33 +01:00
gatecat
18459a9e4c interchange: Handle disconnected/missing cell pins 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-19 10:46:35 +01:00
gatecat
872b3aa63d interchange: Add default cell connections to chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-19 10:16:26 +01:00
gatecat
6fbefb8f13
Merge pull request #681 from YosysHQ/gatecat/more-pybindings 
Add Python bindings for placement tests
 2021-04-15 11:16:31 +01:00
gatecat
1631cdffb8
Merge pull request #680 from YosysHQ/gatecat/fix-util 
Fix utilisation report when bel buckets are used
 2021-04-15 10:14:19 +01:00
gatecat
d4aac6586c Add Python bindings for placement tests 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-15 10:00:45 +01:00
gatecat
d14db5c98f Fix utilisation report when bel buckets are used 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-15 09:24:27 +01:00
gatecat
8f5185c381
Merge pull request #678 from acomodi/initial-fasm-generation 
interchange: add FASM generation target and clean-up tests
 2021-04-14 14:28:01 +01:00
Alessandro Comodi
ea9e12b6ae gh-actions: increase python-fpga-interchange tag version 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-04-14 14:36:47 +02:00
Alessandro Comodi
dfc9c3df8c interchange: add FASM generation target and clean-up tests 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-04-14 14:36:07 +02:00
gatecat
b26088f940
Merge pull request #679 from YosysHQ/gatecat/disable-absl 
Hash table changes
 2021-04-14 12:19:10 +01:00
gatecat
b0f57d234f ci: Re-enable abseil for interchange CI 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-14 10:30:53 +01:00
gatecat
4e346ecfba Hash table refactoring 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-14 10:30:19 +01:00
gatecat
2912860c97
Merge pull request #677 from YosysHQ/gatecat/ppip-no-input 
interchange: Allow pseudo-cells with no input pins
 2021-04-13 11:49:48 +01:00
gatecat
06e54f08e6 interchange: Allow pseudo-cells with no input pins 
These are used for the LUT-as-GND-driver pseudo-pips in the Nexus arch,
which will probably be required for UltraScale too.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-13 10:58:41 +01:00
gatecat
423da76ff2
Merge pull request #676 from YosysHQ/gatecat/fix-sta-crash 
timing: Fix domain init when loops are present
 2021-04-13 10:34:14 +01:00
gatecat
ece10c3e04 timing: Fix domain init when loops are present 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-13 09:23:08 +01:00
gatecat
5cd2a7f9c2
Merge pull request #674 from adamgreig/heap-spreader-fix 
HeAP: Skip high-strength cells in both cell loops
 2021-04-12 14:16:22 +01:00
gatecat
dc6453b720
Merge pull request #673 from YosysHQ/gatecat/fix-fast-bels-ref 
fast_bels: Don't return pointer that might become invalid
 2021-04-12 13:54:11 +01:00
Adam Greig
2fdf41ac01
HeAP: Skip high-strength cells in both cell loops. 
Previously only the first loop skipped cells with high belStrength,
but they can't be processed by the second loop either, so skip them
there too.
 2021-04-12 13:42:20 +01:00
gatecat
fc15105643 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-12 10:26:39 +01:00
gatecat
5b35329abb fast_bels: Don't return pointer that might become invalid 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-12 10:23:41 +01:00
gatecat
b5731cee02
Merge pull request #668 from YosysHQ/gatecat/cell-bel-name-vcc 
interchange: Disambiguate cell and bel pins when creating Vcc ties
 2021-04-09 14:33:12 +01:00
gatecat
9cc09207fc
Merge pull request #669 from YosysHQ/gatecat/prjoxide-pin 
interchange: Pin prjoxide commit in CI
 2021-04-09 11:37:54 +01:00
gatecat
7acef00443 interchange: Pin prjoxide commit 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-09 11:17:25 +01:00
gatecat
93e34b8754 interchange: Disambiguate cell and bel pins when creating Vcc ties 
The pins created for tieing to Vcc were being named after the bel pin,
relying on the fact that Xilinx names cell and bel pins differently for
LUTs. This isn't true for Nexus devices which uses the same names for
both, and was causing a failure as a result.

This uses a "PHYS_" prefix that's highly unlikely to appear in a cell
pin name to disambiguate.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-09 10:26:32 +01:00
Miodrag Milanović
581682a08e
Merge pull request #667 from YosysHQ/fix_qt 
Add same fix as in issue #373
 2021-04-08 13:40:44 +02:00
Miodrag Milanovic
157cc1b60c Add same fix as in issue #373 2021-04-08 12:33:34 +02:00
gatecat
883ece6034
Merge pull request #665 from cr1901/optional-lto 
Add CMake option to enable IPO (enabled by default).
 2021-04-07 12:21:23 +01:00
William D. Jones
2cb2985539 Add CMake option to enable IPO (enabled by default). 2021-04-07 06:25:29 -04:00
gatecat
31eda82b3f
Merge pull request #659 from litghost/pseudo_pip_fixes 
[interchange] Pseudo pip fixes
 2021-04-06 20:08:37 +01:00
gatecat
8501098c16
Merge pull request #663 from litghost/fix_router2_without_bb 
Fix bug in router2 where router may give up too early.
 2021-04-06 19:35:55 +01:00
Keith Rothman
ae2f7551c1 [interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
c43ad2fab6 Don't fail-fast for GH actions to allow for easier CI debugging. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
3200026e1f [interchange] Remove requirement to have wire_lut. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
c2a6f6ce62 [interchange] Fix invalid use of local variables due to refactoring. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
8773c645ca [interchange] Prevent site router from generating incorrect LUTs. 
The previous logic tied LUT input pins to VCC if a wire was unplacable.
This missed a case where the net was present to the input of the LUT,
but a wire was still not legal.  This case is now prevented by tying the
output of the LUT to an unused net.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
c11ad31393 [interchange] Scale edge cost of pseudo pips. 
Previous pseudo pips were the same cost as regular pips, but this is
definitely too fast, and meant that the router was prefering them.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00