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865 Commits

Author SHA1 Message Date
Sylvain Munaut
9c5f4fb885 ice40/pll: Fix typo when testing for global port output net 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-20 23:53:08 +01:00
Sylvain Munaut
e8556aff37 ice40: Add support for SB_RGBA_DRV 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
de8de6304f ice40: Add global network output support for LFOSC/HFOSC 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
271cc7be11 ice40/pack: Add helper to constain cells that are unique in the FPGA 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
519d4e2af8 ice40: Add support for SB_GB_IO 
During packing we replace them by standard SB_IO cells and create the
'fake' SB_GB that matches that IO site global buffer connection.

It's done in a separate pass because we need to make sure the nextpnr iob
have been dealt first so we have our final Bel location on the SB_IO.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
d8e4c21d96 ice40: Add support for PLL global outputs via PADIN 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
bc9f2da470 ice40: Introduce the concept of forPadIn SB_GB 
Those are cells that are created mainly to handle the various sources a
global network can be driven from other than a user net.

When the flag is set, this means the global network usually driven by
this BEL is in fact driven by something else and so that SB_GB BEL and
matching global network can't be used.

This is also what gets used to set the extra bits during bitstream
generation.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
325d46e284 ice40/chipdb: Add wires to global network for all cells that can drive it 
The icebox DB is a bit inconsistent in how global network connections
are represented. Here we make it appear consistent by creating ports
on the cells that can drive it.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
3f4dc7c80e ice40: Add GlobalNetowkrInfo in the chip database 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
c219d8fe4d ice40: Fix BEL validity check for PLL vs SB_IO 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
9483a95a4a ice40: Improve the is_sb_pll40_XXX predicates collection 
- Add a test for dual output PLL variant
 - Make them handle the packet version of the cell

 This will become useful for various tests during PLL rework

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
f6d6022984 ice40: Fix PLLTYPE for SB_PLL40_2F_PAD 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
ad23caef33 ice40/pll: Add proper support for PLLOUT_SELECT_xxx attributes 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
78f3c2c37d ice40: Make PLL default FEEDBACK_MODE to SIMPLE 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
35e9ec7737 ice40: Minor fix in predicate checking for logic port 
- is_sb_pll40 covers all the PLL types
 - Use helper to test for gbuf

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
ac5d767d4f ice40/pack: Stop looking for BEL when we have one during PLL placement 
Ideally we should first process all the PLL that are constrained somehow
(either explicitely or because they are PAD) and then free place the rest.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
5fb3353557 ice40/pack: Allow PLL to be constrained via 'BEL' attributes 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
8c69a3bba3 ice40/pack: Make sure we don't use a LOCKED bel when placing PLL 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
b29165eeba ice40/arch: Add helper to check if a BEL is LOCKED or not 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
70e1fe423f ice40/chipdb: Fix LOCKED keyword support to include all packages 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 13:12:43 +01:00
Sylvain Munaut
42fbb110fc ice40/bitstream: Handle IoCtrl.IE_ polarity when configuring unused SB_IO 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 13:12:43 +01:00
Sylvain Munaut
e1e8d8cd14 ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhere 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-16 16:36:57 +01:00
Sylvain Munaut
01950a2349 ice40/bitstream: Convert to UNIX line endings 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-16 16:24:56 +01:00
David Shah
9c52afcf5f clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:25:51 +00:00
David Shah
20aa0a0eed ice40: Remove unnecessary RAM assertion 
Fixes #121

Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:18:53 +00:00
Eddie Hung
c5ba77e06b Merge remote-tracking branch 'origin/master' into timingapi 2018-11-13 13:47:37 -08:00
Eddie Hung
51a2894762 [ice40] getBudgetOverride() to use constrained Z not placed Z 2018-11-13 12:51:46 -08:00
Eddie Hung
2d39cde17b Merge remote-tracking branch 'origin/master' into timingapi 2018-11-13 12:12:11 -08:00
Eddie Hung
3b2b15dc4a
Merge pull request #107 from YosysHQ/router_improve 
Major rewrite of "router1"
 2018-11-13 11:39:51 -08:00
Pedro Vanzella
710ea1b265 Mark getArchOptions as override in derived classes 2018-11-13 11:03:48 -02:00
Clifford Wolf
06e0e1ffee Various router1 fixes, Add BelId/WireId/PipId::operator<() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-13 05:05:56 +01:00
David Shah
fc5e6bec9a timing: Add support for clock constraints 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
07e265868b archapi: Add getDelayFromNS to improve timing algorithm portability 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
e633aa09cc timing: Fix handling of clock inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
9687f7d1da Working on multi-clock analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
122771cac3 timing: iCE40 Arch API changes for clocking info 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
becf3021bd ice40: Don't set colbuf bits for 384 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-11-11 23:52:04 +01:00
Clifford Wolf
6002a0a80a clangformat 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 19:48:15 +01:00
Clifford Wolf
f93129634b Add getConflictingWireWire() arch API, streamline getConflictingXY semantic 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 17:28:41 +01:00
Clifford Wolf
d2bdb670c0 Add getConflictingPipWire() arch API, router1 improvements 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 11:34:38 +01:00
Miodrag Milanović
6b197fde72
Merge pull request #93 from YosysHQ/gui_changes 
Gui changes
 2018-11-10 23:00:34 -08:00
David Shah
8df72a1f34 ice40: Fix SPRAM and IO globals 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-04 14:13:53 +00:00
David Shah
af9ed378b4 ice40: Fix PLL DYNAMICDELAY 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-27 23:28:25 +02:00
Miodrag Milanovic
4c0db11608 fix grid dimensions for ice40 2018-10-27 12:02:01 +02:00
Miodrag Milanovic
69b9aaba9d ups, uncomment 2018-10-27 11:52:29 +02:00
Miodrag Milanovic
61b2fcf7da Fixed pip graphics 2018-10-27 11:50:40 +02:00
Eddie Hung
96efe48847
Merge pull request #88 from YosysHQ/issue72 
Resolve issue #72
 2018-10-11 02:54:19 -07:00
Clifford Wolf
b4dc6b8845 Add info message for promoted global nets 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-03 13:40:21 +02:00
David Shah
7ef8a7415d ice40: Add error for bad PACKAGE_PIN connections 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-03 12:14:49 +01:00
David Shah
a27c7b45de Refactor chain finder to its own file 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 16:29:26 +01:00
David Shah
ea03aafc26 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 15:13:18 +01:00
Clifford Wolf
07cf349ee4
Merge pull request #79 from YosysHQ/ice40lvds 
ice40: Adding LVDS input support
 2018-09-25 18:21:56 +02:00
Clifford Wolf
1eb7411fb0
Merge pull request #76 from YosysHQ/plloutglobal_fix 
Add needed PLLOUTGLOBAL ports and mapped it
 2018-09-25 18:15:00 +02:00
David Shah
f1aa7093fe ice40: Fix carry packer bug 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-25 15:52:32 +01:00
David Shah
dea87e46c4 ice40: LVDS input bitstream support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 17:58:55 +01:00
David Shah
2ee86ab5a8 ice40: Tristate IO support fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 15:25:37 +01:00
David Shah
d5d9fb27a6 ice40: Validity check for LVDS IO 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 15:14:28 +01:00
David Shah
9834b68041 ice40: Remove obsolete belType member 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 14:27:50 +01:00
Miodrag Milanovic
f8e258825f Added required checks for PLL and fixed messages eol 2018-09-19 18:41:28 +02:00
Eddie Hung
c9059fc7d0 [ice40] TimingPortClass of LC.O ports without any inputs now TMG_IGNORE 2018-09-15 15:16:21 -07:00
Miodrag Milanovic
fdf7593c42 Add needed PLLOUTGLOBAL ports and mapped it properly 2018-09-12 18:33:08 +02:00
Serge Bazanski
8ed64450f3
Merge pull request #56 from YosysHQ/q3k/issue-55 
ice40: make PLL packing more robust
 2018-08-19 21:37:02 +01:00
Sergiusz Bazanski
1bf22a7f64 ice40: make PLL packing more robust 2018-08-19 21:30:55 +01:00
Clifford Wolf
801f630983 Add more missing iCE40 gfx (LP/HX is complete now) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 18:43:38 +02:00
Clifford Wolf
49d3857f97 Add iCE40 gfx for carry chain pips and LUT cascade pips 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 17:55:54 +02:00
Clifford Wolf
e45769292a Fix iCE40 pip gfx for pips on the top edge of a switchbox 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 17:23:21 +02:00
Clifford Wolf
b7d4c7afd9 Add iCE40 gfx for IO span-4 corners 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 16:53:34 +02:00
Clifford Wolf
7cdafb8121 Add iCE40 gfx for span-4 wires between IO tiles 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 16:31:02 +02:00
Clifford Wolf
26be6f9761
Merge pull request #47 from YosysHQ/settings_propagate 
Use settings for placer1 and router1
 2018-08-18 19:25:19 +02:00
Clifford Wolf
a346793c19 Add iCE40 gfx for wires connecting fabric tiles and IO tiles 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-18 17:17:01 +02:00
Clifford Wolf
456a83430a Improve iCE40 gfx for IO tiles and RAM tiles 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-18 16:20:33 +02:00
Clifford Wolf
5500cf3aff Add ice40 wire attributes (grid position, segment list) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-18 14:14:27 +02:00
Clifford Wolf
97520bb728 Merge branch 'master' of github.com:YosysHQ/nextpnr into archattr 2018-08-18 13:06:21 +02:00
Miodrag Milanovic
3c51007026 do not break if there are no nets loaded from sym section 2018-08-18 10:28:50 +02:00
Clifford Wolf
428f0b9eba Add Arch attrs API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-14 17:16:14 +02:00
Eddie Hung
fc0496ec71 Merge remote-tracking branch 'origin/master' into placer_speedup 2018-08-10 19:51:35 -07:00
Eddie Hung
a41500a015 Rework Arch::logicCellsCompatible() to take pointer + size, allowing use of std::array 2018-08-10 19:50:27 -07:00
Miodrag Milanovic
e5006d4f2f Save settings and give nicer names to some 2018-08-10 19:11:30 +02:00
Eddie Hung
396cae5118 Make containers static 2018-08-09 20:53:33 -07:00
Miodrag Milanovic
93a0d24560 Use settings for placer1 and router1 2018-08-09 18:39:10 +02:00
David Shah
ed602baa06
Merge pull request #42 from YosysHQ/floorplan 
Add basic data structures for floorplanning
 2018-08-09 10:49:11 +02:00
Clifford Wolf
5ddde5c49f Add pip locations 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-09 10:39:53 +02:00
Eddie Hung
41e05c95aa ice40: Speedup Arch::predictDelay() with pass-by-ref 2018-08-08 19:52:39 -07:00
Miodrag Milanovic
61bce47f3c Use settings for json and pcf 2018-08-08 20:14:18 +02:00
Clifford Wolf
f6189e4677 Merge branch 'master' of github.com:YosysHQ/nextpnr into constids 2018-08-08 19:35:13 +02:00
David Shah
cd4e761bb7
Merge pull request #44 from YosysHQ/improve_timing_spec 
Speed up budget allocator using topographical ordering and update cell timing API
 2018-08-08 19:23:47 +02:00
Miodrag Milanovic
46aa56021b Moved option to common 2018-08-08 18:34:12 +02:00
Miodrag Milanovic
fc5cee6fb8 clangformat 2018-08-08 18:17:34 +02:00
David Shah
751335977f ice40: Add error for unknown cell type when getting timing info 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 18:07:34 +02:00
Clifford Wolf
f875a37467 Get rid of old iCE40 id_ Arch members 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-08 17:17:16 +02:00
David Shah
433ad6462e Arch API: Removing Arch::isIOCell 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 17:06:59 +02:00
Clifford Wolf
e03ae50e21 Get rid of PortPin and BelType (ice40, generic, docs) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-08 17:01:18 +02:00
David Shah
e6eb203868 ice40: Add timing arcs through global buffers 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 16:34:41 +02:00
David Shah
d173ddba36 timing: Debugging implementation of new timing API 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 15:15:21 +02:00
David Shah
787fe5661c ice40: Timing arch fix 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 15:00:39 +02:00
David Shah
d8b3830031 timing: Update to new use API (currently broken) 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 14:58:43 +02:00
David Shah
bf42e525cb Arch API: New specification for timing port classes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 14:37:59 +02:00
Miodrag Milanovic
5df90bc5a5 Merge remote-tracking branch 'origin/master' into common_main 
# Conflicts:
#	ecp5/main.cc
#	ice40/main.cc
 2018-08-08 10:48:05 +02:00
Eddie Hung
f44a5fb904 clangformat 2018-08-06 17:35:23 -07:00
Eddie Hung
1b9a664bb1 Merge branch 'master' into assign_budget_speedup 2018-08-06 12:30:24 -07:00
Eddie Hung
9addcac09c ice40's getBudgetOverride() to return correct delay for different devices 2018-08-06 12:22:13 -07:00
Eddie Hung
21cd1d7dd6 Add new Arch::isIOCell() API function 2018-08-06 12:11:47 -07:00
Miodrag Milanovic
fffaaa613f Added project loader 2018-08-06 19:32:17 +02:00
Eddie Hung
0f3459dbe5 Fix ice40's getBudgetOverride() to override only for COUT -> CIN 2018-08-06 08:22:08 -07:00
Eddie Hung
823ceaacbf Change getBudgetOverride() signature to return bool and modify budget in place 2018-08-06 07:56:28 -07:00
Eddie Hung
f048deb33d Restore initial assign_budget() call after pack(), restrict call after initial_placement to slack_redist 2018-08-05 22:55:58 -07:00
David Shah
1ce0b5add2 API change: Use CellInfo* and NetInfo* as cell/net handles (Python bindings) 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-05 16:21:13 +02:00
Miodrag Milanovic
7794bbfb3f Fix message for pcf loading 2018-08-05 16:13:49 +02:00
Miodrag Milanovic
3bb9a7df01 Added command parser and common implementation 2018-08-05 16:13:34 +02:00
Clifford Wolf
5e53075990 API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-05 15:25:42 +02:00
Clifford Wolf
287fe7e894 clangformat 2018-08-05 14:18:34 +02:00
Clifford Wolf
528eddcaf7 Fix bug in ice40 estimateDelay() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 22:29:43 +02:00
Clifford Wolf
175da732ac Use faster model for ice40 predictDelay() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 20:16:43 +02:00
Clifford Wolf
f6b3333a7d Add new iCE40 delay estimator and delay predictor 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 19:50:49 +02:00
David Shah
67347573c2 ice40: Bitstream gen for LUT permutation 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-04 18:23:48 +02:00
Clifford Wolf
31fe52581b Add generation of models to tmfuzz 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 16:54:12 +02:00
Clifford Wolf
bd36cc1275 Refactor ice40 timing fuzzer used to create delay estimates 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 13:41:42 +02:00
Clifford Wolf
700e68746a Fix bug in ice40 chipdby.py add_wire() that moves some wires to X0/Y0 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 13:33:24 +02:00
Clifford Wolf
086bc941a8 Remove SVG functionality from ice40 main 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 11:52:35 +02:00
Clifford Wolf
96291f17aa Merge branch 'master' of github.com:YosysHQ/nextpnr into lutperm 2018-08-04 10:32:07 +02:00
Eddie Hung
d66edf5223 Merge branch 'master' into slack_redist_freq 2018-08-03 23:43:53 -07:00
David Shah
65d73eb983
Merge pull request #23 from daveshah1/use_placeconstr 
Making use of relative constraints
 2018-08-04 08:32:42 +02:00
David Shah
affc6da1af ice40: Add SB_GB timing to database 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-04 08:28:13 +02:00
David Shah
082b8bf272 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-04 08:18:04 +02:00
David Shah
176a23936c Tidy up 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-04 08:15:49 +02:00
Eddie Hung
3d5dcda12c Auto frequency only if --freq 0 is set 2018-08-03 19:53:32 -07:00
Clifford Wolf
8d372b86f3 Proper ice40 wire types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-03 21:11:12 +02:00
David Shah
b937e6defe Add constraint weight as a command line option 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 18:31:54 +02:00
Clifford Wolf
2a1d54389f Add iCE40 pseudo-pips for lut permutation 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-03 17:37:59 +02:00
David Shah
fd2174149c Fixing constraint placement bugs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 16:29:44 +02:00
David Shah
8c518cb838 Fixing relative constraint implementation 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 15:40:01 +02:00
David Shah
7e9209878c Reworking packer and placer to use new generic rel legaliser 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 15:00:32 +02:00
David Shah
26c68c4bcc Remove old place legaliser, set placement constraints instead (currently ignored by placer) 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 13:18:48 +02:00
Clifford Wolf
80e6b17ec9
Merge pull request #21 from daveshah1/promote_logic_globals 
ice40: Promote 'logic' globals as well as clock/enable/reset
 2018-08-03 12:51:55 +02:00
Clifford Wolf
e673d9d2db
Merge pull request #22 from YosysHQ/routethru 
Add iCE40 LUT route-through pips
 2018-08-03 12:51:37 +02:00
David Shah
483f1b772c ice40: Promote 'logic' globals as well as clock/enable/reset 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 09:56:56 +02:00
David Shah
35bc80e130 ice40: Add bitstream gen for routethru LUTs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 09:26:37 +02:00
Miodrag Milanovic
a761b772c8 Make worker generic 2018-08-02 18:10:01 +02:00
Miodrag Milanović
e46209e734
Merge pull request #11 from mmicko/project_load 
preserve command line parameters for project load
 2018-08-02 08:24:49 -07:00
Clifford Wolf
36009645ce Add LUT route-through pips to iCE40 architecture database 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-02 16:28:47 +02:00
David Shah
a7269a685e ice40: Use real cell timings 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-02 16:02:51 +02:00
David Shah
c0aaac8dfa ice40: Adding cell timings to chipdb 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-02 15:20:43 +02:00
Clifford Wolf
6ccf8629b5 Add Router1Cfg 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-02 13:58:23 +02:00
Miodrag Milanovic
869a804ee1 preserve command line parameters for project load 2018-08-02 06:29:21 +02:00
Clifford Wolf
29dd98420b Remove getFrameDecal() API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-01 11:30:11 +02:00
David Shah
0414c93403 ice40: Add HFOSC support, force fabric routing on oscillators for now 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-01 09:45:08 +02:00
David Shah
bbd2ecf558 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-01 09:33:52 +02:00
Miodrag Milanovic
009bed51cb Display warning only if gui is not used 2018-08-01 08:26:50 +02:00
Miodrag Milanovic
8293569c32 Fix filenames for MSVC build 2018-08-01 08:16:38 +02:00
David Shah
b1a9978922 Merge branch 'redist_slack' into 'master' 
Update budgets throughout placement and routing

See merge request SymbioticEDA/nextpnr!16
 2018-08-01 05:59:34 +00:00
Eddie Hung
92ec2cd138 clangformat for stuff I've touched 2018-07-31 20:57:36 -07:00
Sergiusz Bazanski
85fc356fc1 clangformat 2018-08-01 03:59:27 +01:00
Eddie Hung
f646ec790a Modify the getNetinfo*() functions and getBudgetOverride() to not use 
user_idx and to take a PortRef& instead
 2018-07-31 19:31:54 -07:00
Eddie Hung
720e815865 Add --slack_redist_iter for ice40 2018-07-31 19:07:39 -07:00
Eddie Hung
5d58d6ad1b Merge branch 'redist_slack' of gitlab.com:SymbioticEDA/nextpnr into redist_slack 2018-07-31 18:26:39 -07:00
Eddie Hung
2d75053744 Merge remote-tracking branch 'origin/estdelay' into redist_slack 
Conflicts:
	ecp5/arch.cc
	generic/arch.cc
	ice40/arch.cc
 2018-07-31 16:18:08 -07:00
Eddie Hung
70747b9355 Merge branch 'redist_slack' into 'redist_slack' 
# Conflicts:
#   common/timing.cc
 2018-07-31 17:51:56 +00:00
Clifford Wolf
41726087b7 getChipName() should be const 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-31 17:01:38 +02:00
Clifford Wolf
2652485a01 Use icestorm timing information 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-31 16:43:19 +02:00
Clifford Wolf
32ff0059fe Add binary search to getBelPinWire() and getBelPinType() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-31 11:55:25 +02:00
Eddie Hung
07e2c9ba99 assign_budget() after initial placement, not after pack 2018-07-30 22:20:49 -07:00
Eddie Hung
a82f6f4105 Modify predictDelay signature 2018-07-30 21:51:30 -07:00
Eddie Hung
a099aca3c2 Modify predictDelay signature 2018-07-30 19:19:30 -07:00
Eddie Hung
d5049bf0ed Merge remote-tracking branch 'origin/estdelay' into redist_slack 2018-07-30 18:59:04 -07:00
Eddie Hung
46b7469652 Merge remote-tracking branch 'origin/master' into redist_slack 2018-07-30 18:14:40 -07:00
Clifford Wolf
b121008372 Towards better ice40 timing data 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-30 17:17:07 +02:00
David Shah
b09183db3b Use DelayInfo for cell timing instead of delay_t 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-30 16:59:30 +02:00
David Shah
84e0082925 cmake: Set --fast and --slow chipdb.py arguments 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-30 16:40:56 +02:00
Clifford Wolf
3d8b0087c3 Add ice40 chipdb.py --fast/--slow 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-30 16:36:34 +02:00
Clifford Wolf
8f9b031ef0 Add iCE40 fast/slow delay fields to chipdb 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-30 16:21:20 +02:00
David Shah
267970c01e ice40: Improving legalisation move statistics 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-30 16:18:49 +02:00
David Shah
edc6cf8b23 ice40: Print legalisation statistics 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-30 16:13:02 +02:00
Clifford Wolf
0daffec2a0 Add predictDelay Arch API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-30 15:35:40 +02:00
Clifford Wolf
0db86b8619 Improve ice40/benchmark 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-30 13:57:14 +02:00
Eddie Hung
beabb429b0 clangformat 2018-07-28 14:11:43 -07:00
Eddie Hung
02b3bda7f6 ice40 estimateDelay to account for out/in muxes 2018-07-27 19:52:45 -07:00
Eddie Hung
cd561b4316 getBudgetOverride() now handles COUT crossing tiles 2018-07-26 22:30:15 -07:00
Eddie Hung
97e546041e Revert "Remove Arch::getBudgetOverride()" 
This reverts commit 749dae4ae5.
 2018-07-26 21:37:19 -07:00
Eddie Hung
d5c2332ebf Merge remote-tracking branch 'origin/master' into redist_slack 2018-07-26 21:00:26 -07:00
Sergiusz Bazanski
c37d2baaf6 common: rename GraphicElement::{style,type} enums, add _MAX members 2018-07-26 16:39:19 +01:00
Clifford Wolf
03f92948d1 clangformat and GraphicElement::style comments 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-26 17:14:56 +02:00
Clifford Wolf
467e0926f9 Add getWireType()/getPipType() API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-26 16:38:11 +02:00
Clifford Wolf
6a59b8522c Move iCE40 switchbox gfx to UI groups 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-26 16:21:01 +02:00
Clifford Wolf
7152ae1e3d Add iCE40 pip gfx for carry_in mux 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-26 15:42:32 +02:00
Clifford Wolf
a86c4f2f5d Improvements in bbasm 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-26 15:22:52 +02:00
Eddie Hung
749dae4ae5 Remove Arch::getBudgetOverride() 2018-07-25 23:02:31 -07:00
Eddie Hung
e2f8deec41 clangformat 2018-07-25 18:22:23 -07:00
Eddie Hung
a21cc4dd5b Merge remote-tracking branch 'origin/master' into redist_slack 2018-07-25 17:55:20 -07:00
Eddie Hung
950f33c1bb clangformat 2018-07-25 17:53:01 -07:00
Eddie Hung
e6015dc695 Merge remote-tracking branch 'origin/master' into eddieh/idstring_speedup 2018-07-25 17:51:47 -07:00
Eddie Hung
7c8c13aba1 Merge remote-tracking branch 'origin/master' into redist_slack 2018-07-25 17:41:23 -07:00
Clifford Wolf
a8001daf6f Add ice40/benchmark/report.ipynb 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-25 16:26:08 +02:00
Clifford Wolf
cc6e0e7df3 More minor ice40 benchmark improvements 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-25 15:51:19 +02:00
David Shah
1529fbe58c ice40: Tweaking picorv32_benchmark.py 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-25 15:49:43 +02:00
Clifford Wolf
6ea898855c Minor improvements in iCE40 benchmark scripts 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-25 14:02:22 +02:00
Clifford Wolf
5db4a3e8b0 Add ice40/benchmark/ 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-25 13:28:12 +02:00
Clifford Wolf
f3dab003e7 Merge branch 'bba' into 'master' 
bbasm

See merge request SymbioticEDA/nextpnr!18
 2018-07-25 11:07:51 +00:00
Sergiusz Bazanski
2c34a50a7c ice40: after review 2018-07-25 12:01:51 +01:00
Sergiusz Bazanski
db4f2d2318 ice40: check PLL PACKAGEPIN drives only PLL, cosmetics 2018-07-25 11:47:24 +01:00
Sergiusz Bazanski
14a501969a Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/pll-pads 2018-07-25 11:32:45 +01:00
Sergiusz Bazanski
c554ab1ef0 clang-format 2018-07-25 11:32:40 +01:00
Sergiusz Bazanski
aad0d3eb35 ice40: support PLL40_*_PAD, fix pass-through LUT for LOCK 2018-07-25 11:32:21 +01:00
Miodrag Milanovic
6ac2a4de48 proper options for linux build 2018-07-25 12:13:06 +02:00
David Shah
e39290b712 Add a simple 8x benchmark script 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-25 10:48:24 +02:00
Eddie Hung
c71212d0e1 If --freq not set, attempt to find max by adjusting budget so min path slack == 0 2018-07-24 23:19:24 -07:00
Eddie Hung
9382938661 Merge branch 'master' into redist_slack 2018-07-24 22:20:10 -07:00
Eddie Hung
879f0d7c57 Reduce id() lookups for commonly used update_budget() 2018-07-24 21:21:11 -07:00
Clifford Wolf
c3859072d4 Use bbasm to create iCE40 chipdb 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-24 21:10:42 +02:00
Sergiusz Bazanski
2039112a47 ice40: after review 2018-07-24 15:59:18 +01:00
Sergiusz Bazanski
b31e95f82c Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/pll 2018-07-24 15:54:03 +01:00
David Shah
974ca143e8 Remove implementations of deprecated APIs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-24 16:09:29 +02:00
David Shah
5a170f286c ice40: Remove use of deprecated APIs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-24 15:52:56 +02:00
Clifford Wolf
c0c8dc7602 Remove uphill/downhill bel pins from ice40 db 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-24 15:44:39 +02:00
David Shah
942c552e07 Add bbasm target, use as passthru in iCE40 builder 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-24 15:31:00 +02:00
Clifford Wolf
9d38907e95 Add G_ARROW (for now same look as G_LINE) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-24 12:18:01 +02:00
David Shah
7858663aa7 timing: Model clock to Q times 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-24 11:46:14 +02:00
David Shah
4359197dfe ice40: Trim BRAM constant inputs, reduces routing congestion around BRAM 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-24 11:21:10 +02:00
David Shah
a09f95bb06 ice40: Fix SPRAM and other primitives in corners other than (0, 0) 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-24 11:16:33 +02:00
Sergiusz Bazanski
90ba958abe ice40: fixes before review 2018-07-24 03:19:22 +01:00
Sergiusz Bazanski
eaae1d299c ice40: move PLL->IO from pseudo pip to second uphill bel 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
65ceb20784 ice40: emit list of upbels in chipdb 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
fae7994bc3 clang-format 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
dbf79d78bb ice40: A slightly nicer way to do this. 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
065ea95eab ice40: Move spliceLUT back to pack.cc 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
1d3147e26a ice40: Prevent placement of SB_IOs in IO blocks used by PLL outputs 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
e6c7b14465 ice40: Refactor PLL/LOCK LUT splicing out into Arch:: 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
69233385f8 ice40: Emit feed-through LUTs for PLL/LOCK 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
db31c0625b ice40: Fail early on SB_PLL40_*_PAD cells 2018-07-24 02:55:38 +01:00
Sergiusz Bazanski
2b1f7875bb ice40: Implement emitting PLLs 2018-07-24 02:38:10 +01:00
Eddie Hung
771edd1fda Merge branch 'master' into redist_slack 2018-07-23 07:16:39 -07:00
Clifford Wolf
e647604e2a Add Context::archcheck() and "nextpnr-ice40 --test" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-23 14:03:23 +02:00
Clifford Wolf
90fe002a36 Remove getBelsByType() API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-23 13:16:27 +02:00
David Shah
bfa1137fe0 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-23 13:02:57 +02:00
Clifford Wolf
27c5236826 Add getGridDimX(), getGridDimY(), getTileDimZ() API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-23 12:19:54 +02:00
Clifford Wolf
3788bd26e6 Bugfix in iCE40 chipdb.py 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-23 00:25:49 +02:00
Miodrag Milanovic
b9c413a5aa Move to new API and remove deprecated 2018-07-22 19:58:17 +02:00
Clifford Wolf
e13fc7edab Add Arch::getBelPins() to generic and iCE40 archs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 12:08:52 +02:00
Clifford Wolf
b60c9485d2 Add Arch::getBelPinType() and Arch::getWireBelPins() in iCE40 arch 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 11:56:51 +02:00
Clifford Wolf
62b66e0208 Rename getWireBelPin to getBelPinWire 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 10:59:21 +02:00
Clifford Wolf
1e96999863 clangformat 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 00:50:49 +02:00
Eddie Hung
926c186ec7 Add Arch::getBudgetOverride() to eliminate hack for COUT 2018-07-21 13:05:09 -07:00
Clifford Wolf
9e6deed3b8 Merge branch 'q3k/lock-2-electric-boogaloo' into 'master' 
Basic locking and threading for Arch/GUI

See merge request SymbioticEDA/nextpnr!10
 2018-07-21 19:45:24 +00:00
Clifford Wolf
30e2f0e1e8 Add Loc constructors 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-21 21:40:06 +02:00
Sergiusz Bazanski
6588aafdb8 Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-electric-boogaloo 2018-07-21 20:00:42 +01:00
Miodrag Milanovic
f438fc615b Added driver and users for nets 2018-07-21 20:21:48 +02:00
Clifford Wolf
39b843ecac Merge branch 'router1ng' into 'master' 
Router1ng

See merge request SymbioticEDA/nextpnr!13
 2018-07-21 17:59:44 +00:00
Miodrag Milanovic
3175891cb5 Map ports to nets 2018-07-21 19:48:00 +02:00
Miodrag Milanovic
57c63e6921 create io cells out of asc 2018-07-21 17:54:35 +02:00
Miodrag Milanovic
912a79dc33 add cells that are in default state or no configuration 2018-07-21 17:38:22 +02:00
Miodrag Milanovic
7beb4739d4 Add used cells and attach them to bels 2018-07-21 17:04:47 +02:00