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Author SHA1 Message Date
gatecat
e069b3bc6a
Merge pull request #900 from antmicro/nexus-osc-tolerance 
Honor nexus OSCA frequency tolerance
 2022-01-28 19:19:33 +00:00
Maciej Kurc
e51e82d6a9 Added honoring OSCA output frequency tolerance during constraints generation 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-01-28 13:51:10 +01:00
gatecat
1301feb4ad
Merge pull request #899 from antmicro/nexus-dsp-packing 
Fix for Nexus DSP packing
 2022-01-25 12:30:39 +00:00
Maciej Kurc
18f71ace8c Removed the need for MULT36_CORE bel for implementing the MULTADDSUB9X9WIDE macro 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-01-25 12:08:52 +01:00
gatecat
fbeef2b8c2
Merge pull request #895 from galibert/master 
Sync with the current state of mistral
 2022-01-19 13:22:40 +00:00
Olivier Galibert
27d38de612 Mistral: Use log_error, remove leftover debugging printf. 2022-01-19 08:42:29 +01:00
Olivier Galibert
91a0eb9367 Mistral: fix gpio OE, add hmc bypass support 2022-01-18 22:37:35 +01:00
Olivier Galibert
b5fc788153 Sync with the current state of mistral 2022-01-18 15:12:45 +01:00
gatecat
58a1b473b8
Merge pull request #873 from YosysHQ/gatecat/ice40-carry-lut 
ice40: Pack LUT at start of carry chain if there is 1 candidate
 2022-01-16 19:59:56 +00:00
gatecat
2ab08a872d
Merge pull request #894 from antmicro/integer-hashing 
Better hashing function for integer pairs
 2022-01-11 16:33:19 +00:00
Maciej Kurc
ae7c2261be Switched integer pair hashing function from DJB2 to Cantor 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-01-11 15:28:13 +01:00
gatecat
3d24583b91
Merge pull request #893 from YosysHQ/gatecat/viaduct 
Viaduct API for a hybrid between generic and full-custom arch
 2022-01-07 16:16:47 +00:00
gatecat
e88bd34c02 Viaduct API for a hybrid between generic and full-custom arch 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-01-04 20:19:29 +00:00
gatecat
089ca8258e
Merge pull request #892 from yrabbit/off-by-one 
gowin: Fix last MUX2_LUT8
 2022-01-03 12:47:44 +00:00
YRabbit
045ce3f148 gowin: Fix last MUX8 
In fact, there is also an input/output column.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-01-03 17:48:31 +10:00
gatecat
3266c51d85
Merge pull request #890 from YosysHQ/gatecat/ssoarray-move 
SSOArray: Implement move and assignment operators
 2021-12-31 06:57:25 +00:00
gatecat
69a4e3e544 SSOArray: Implement move and assignment operators 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-30 21:32:24 +00:00
gatecat
d65c629fb0
Merge pull request #889 from YosysHQ/gatecat/generic-refactor 
generic: Refactor for faster performance
 2021-12-30 13:12:20 +00:00
gatecat
59874188a6 generic: Refactor for faster performance 
This won't affect Python-built arches significantly; but will be useful
for the future 'viaduct' functionality where generic routing graphs can
be built on the C++ side; too.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-30 11:54:08 +00:00
gatecat
c272d28e57 docs: Fix typo 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-29 21:43:33 +00:00
gatecat
fdeb86809f
Merge pull request #877 from pepijndevos/patch-3 
Add support for GW1NS-4 series devices
 2021-12-26 19:14:05 +00:00
Pepijn de Vos
5b6961edd0
update release that actually includes GW1NS-4 chipdb 2021-12-26 17:52:00 +01:00
gatecat
4dbf1c1ca4
Merge pull request #888 from yrabbit/dim-xy 
gowin: Initializing the grid dimensions
 2021-12-26 07:39:18 +00:00
YRabbit
e6b7879542 gowin: Initializing the grid dimensions 
gridDimX and gridDimY are not initialized explicitly, which leads to
effects when the design is reloaded, say, from the GUI.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-12-26 12:05:35 +10:00
gatecat
643b697178
Merge pull request #884 from yrabbit/simplified-io-pr 
gowin: Add simplified IO cells processing
 2021-12-24 19:28:41 +00:00
Pepijn de Vos
fa1ef15e47 build on release of apycula with gw1ns-4 support 2021-12-24 17:17:25 +01:00
Pepijn de Vos
b53a921e42 Add support for GW1NS-4 series devices 2021-12-24 17:17:25 +01:00
gatecat
de63b5b09a
Merge pull request #887 from YosysHQ/gatecat/mistral-bit-update 
mistral: Update to latest enum name
 2021-12-22 14:06:33 +00:00
gatecat
2c43ac992f mistral: Update to latest enum name 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-22 13:21:18 +00:00
gatecat
d2e193f257
Merge pull request #885 from antmicro/nexus-slewrate 
nexus: handle SLEWRATE in pdc
 2021-12-21 15:08:32 +00:00
Karol Gugala
500fa6f442 nexus: handle SLEWRATE in pdc 2021-12-20 15:09:03 +01:00
YRabbit
5a76b3cb4d gowin: Add simplified IO cells processing 
Some models have I/O cells that are IOBUFs, and other types (IBUFs and
OBUFs) are obtained by feeding 1 or 0 to the OEN input.  This is done
with general-purpose routing so it's best to do it here to avoid
conflicts.

For this purpose, in the new bases, these special cells are of type IOBS
(IOB Simplified).

The proposed changes are compatible with bases of previous versions of
Apycula and do not require changing .CST constraint files.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-12-20 15:48:38 +10:00
gatecat
62a3e09385
Merge pull request #883 from YosysHQ/gatecat/new-predictdelay 
archapi: Use arbitrary rather than actual placement in predictDelay [breaking change]
 2021-12-19 18:46:10 +00:00
gatecat
ddb084e9a8 archapi: Use arbitrary rather than actual placement in predictDelay 
This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.

A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-19 17:15:15 +00:00
gatecat
56d5507333
Merge pull request #882 from YosysHQ/gatecat/router1-tmg-ripup 
router1: Experimental timing-driven ripup support
 2021-12-18 21:49:48 +00:00
gatecat
4a3847765c
Merge pull request #881 from uis246/regex 
Tidy gowin modification regex
 2021-12-18 21:38:52 +00:00
gatecat
f670de7b52 router1: Experimental timing-driven ripup support 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-18 20:58:44 +00:00
uis
9b2d6c5a67 Clean gowin modification regex 2021-12-18 22:44:08 +03:00
gatecat
673faea230
Merge pull request #880 from YosysHQ/gatecat/router1-heuristic 
router1: Improve timing heuristic
 2021-12-18 19:18:21 +00:00
gatecat
53ce8f3736 router1: Improve timing heuristic 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-18 14:30:48 +00:00
gatecat
f80f56d69f
Merge pull request #879 from YosysHQ/gatecat/nexus-867 
nexus: router1 speedup based on #867
 2021-12-18 13:25:13 +00:00
gatecat
cc603a612b
Merge pull request #878 from YosysHQ/gatecat/fix-876 
frontend: Consider net aliases when uniquifying name
 2021-12-17 15:51:45 +00:00
gatecat
a306860144 nexus: router1 speedup based on #867 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-17 15:06:19 +00:00
gatecat
4451a562ef frontend: Consider net aliases when uniquifying name 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-17 14:51:19 +00:00
gatecat
a120577773
Merge pull request #858 from cr1901/machxo2 
MachXO2 Checkpoint 2
 2021-12-17 07:11:31 +00:00
William D. Jones
064b6d808e clangformat. 2021-12-16 17:09:29 -05:00
William D. Jones
78ce9971ff README.md: Add machxo2 arch to list of (experimental) supported devices. 2021-12-16 16:59:38 -05:00
William D. Jones
4d75792257 machxo2: Remove no-iobs option. It was always enabled and should remain an implementation detail. 2021-12-16 16:59:38 -05:00
William D. Jones
be3788fa30 machxo2: Remove -noiopad option when generating miters for post-pnr verification. 2021-12-16 16:59:38 -05:00
William D. Jones
365a871908 machxo2: Add packing logic to forbid designs lacking FACADE_IO top-level ports. 2021-12-16 16:59:38 -05:00