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156 Commits

Author SHA1 Message Date
Ross Schlaikjer
cba4753c22
Only print filenames for now, default on 2020-08-30 18:19:41 -04:00
Ross Schlaikjer
a8c110b045
Add option to print critical path source code 
In order to make debugging the critical path easier, add an option that
will log the location each net was defined, if known.
If the file that contains the definition is known, and is readable, also
print the part of the source HDL responsible for the signal definition.
 2020-08-30 17:43:29 -04:00
whitequark
e7bb04769d Port nextpnr-{ice40,ecp5} to WASI. 
This involves very few changes, all typical to WASM ports:
  * WASM doesn't currently support threads or atomics so those are
    disabled.
  * WASM doesn't currently support exceptions so the exception
    machinery is stubbed out.
  * WASM doesn't (and can't) have mmap(), so an emulation library is
    used. That library currently doesn't support MAP_SHARED flags,
    so MAP_PRIVATE is used instead.

There is also an update to bring ECP5 bbasm CMake rules to parity
with iCE40 ones, since although it is possible to embed chipdb into
nextpnr on WASM, a 200 MB WASM file has very few practical uses.

The README is not updated and there is no included toolchain file
because at the moment it's not possible to build nextpnr with
upstream boost and wasi-libc. Boost requires a patch (merged, will
be available in boost 1.74.0), wasi-libc requires a few unmerged
patches.
 2020-05-23 20:57:26 +00:00
David Shah
b6158f94f6 svg: Basic SVG graphics rendering 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-15 11:35:51 +00:00
David Shah
abdaa9c8a1 ecp5: Router2 test integration 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:38:30 +00:00
David Shah
fe40094216 Preserve hierarchy through packing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-27 10:44:30 +00:00
David Shah
b100087024 python: Add bindings for hierarchy structures 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-27 10:44:30 +00:00
David Shah
6bf3c261fa First pass at data structures for hierarchy 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-27 10:44:30 +00:00
David Shah
6aaa9f5a3d frontend/base: Functions for port import 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-27 10:44:29 +00:00
David Shah
f2b9cc6d23 sdf: Working on support for CVC 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-24 12:37:07 +01:00
David Shah
4775930e49 sdf: Add basic support for writing SDF files 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-19 19:20:02 +01:00
David Shah
5cd2b55f1f python: Adding helper functions for netlist modification 
Signed-off-by: David Shah <dave@ds0.me>
 2019-09-15 19:30:56 +01:00
David Shah
95540763b9 json: Add support for net aliases 
Signed-off-by: David Shah <dave@ds0.me>
 2019-09-13 17:27:15 +01:00
David Shah
ec48f8f464 ecp5: New Property interface 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-05 17:22:37 +01:00
David Shah
1839a3a770 Major Property improvements for common and iCE40 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-05 14:52:15 +01:00
Miodrag Milanovic
bd694bda19 Switching from std to boost fix crash 2019-07-05 10:22:42 +02:00
Miodrag Milanovic
be47fc3e9a clangformat run 2019-06-25 18:19:25 +02:00
Miodrag Milanovic
92da4a91de Preserve ports 2019-06-21 09:43:47 +02:00
Miodrag Milanovic
8d5724f4fd moved some context variables to settings 2019-06-15 15:23:51 +02:00
Miodrag Milanovic
95280060b8 No need for settings class 2019-06-15 13:09:49 +02:00
Miodrag Milanovic
856760599e Use properties for settings and save in json 2019-06-12 18:34:34 +02:00
Miodrag Milanovic
d9b0bac248 Save top level attrs and store current step 2019-06-07 16:11:11 +02:00
Miodrag Milanovic
78e6631f76 Cleanup 2019-06-07 13:49:19 +02:00
Miodrag Milanovic
1093d7e122 WIP saving/loading attributes 2019-06-07 11:48:15 +02:00
Miodrag Milanovic
d5d8213871 Added support for attributes/properties types 2019-06-01 15:52:32 +02:00
David Shah
f0cd51e6bc generic: Cell timing support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-04 16:34:06 +01:00
David Shah
6fffe24177 generic: GUI Python bindings 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-03 16:08:33 +01:00
David Shah
493d6c3fb9 Add Python helper functions for floorplanning 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
9c52afcf5f clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:25:51 +00:00
Eddie Hung
06ddb632d1 Merge remote-tracking branch 'origin/master' into timingapi 2018-11-14 17:59:21 -08:00
Eddie Hung
6527e3b6ae [common] Fix typo in Loc::operator!=() 2018-11-13 16:33:01 -08:00
Eddie Hung
2d39cde17b Merge remote-tracking branch 'origin/master' into timingapi 2018-11-13 12:12:11 -08:00
Clifford Wolf
e06eef375c Add more nameOf() convenience methods 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-13 16:08:44 +01:00
David Shah
fc5e6bec9a timing: Add support for clock constraints 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
143abc6034 timing: Multiple clock analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
9687f7d1da Working on multi-clock analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
b6312abc5d timing: Implementing parts of new timing API 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-11-12 14:03:58 +00:00
David Shah
83b1c43630 timing: Working on a timing constraint API 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-11-12 14:03:58 +00:00
Clifford Wolf
6b94102e5a Add checkers and assertions to router1 and other improvements 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-10 21:14:50 +01:00
Mateusz Zalega
d03291eeb1 gui: improved FPGAViewWidget::paintGL() performance 
Profiling revealed that memcpy() in QOpenGLBuffer::allocate() had been taking
the most time during paintGL() calls. I've been able to take the CPU usage
down to about 1/4 of its previous values by caching elements in VBOs and
updating them only after subsequent calls to renderGraphicElement().

Signed-off-by: Mateusz Zalega <mateusz@appliedsourcery.com>
 2018-10-23 15:43:51 +02:00
Clifford Wolf
5ddde5c49f Add pip locations 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-09 10:39:53 +02:00
Clifford Wolf
a9b6543361 Add Region struct 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-09 10:39:53 +02:00
Clifford Wolf
f6189e4677 Merge branch 'master' of github.com:YosysHQ/nextpnr into constids 2018-08-08 19:35:13 +02:00
David Shah
cd4e761bb7
Merge pull request #44 from YosysHQ/improve_timing_spec 
Speed up budget allocator using topographical ordering and update cell timing API
 2018-08-08 19:23:47 +02:00
Clifford Wolf
2390f7f59c Add ctx->settings 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-08 18:46:33 +02:00
Clifford Wolf
e03ae50e21 Get rid of PortPin and BelType (ice40, generic, docs) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-08 17:01:18 +02:00
David Shah
bf42e525cb Arch API: New specification for timing port classes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 14:37:59 +02:00
David Shah
a0994d5154 common: Add TimingPortClass 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 10:44:42 +02:00
Clifford Wolf
5e53075990 API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-05 15:25:42 +02:00
Clifford Wolf
bd36cc1275 Refactor ice40 timing fuzzer used to create delay estimates 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 13:41:42 +02:00