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e633aa09cc
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149 Commits

Author SHA1 Message Date
David Shah
e633aa09cc timing: Fix handling of clock inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
9687f7d1da Working on multi-clock analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
122771cac3 timing: iCE40 Arch API changes for clocking info 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
Eddie Hung
96efe48847
Merge pull request #88 from YosysHQ/issue72 
Resolve issue #72
 2018-10-11 02:54:19 -07:00
David Shah
ea03aafc26 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 15:13:18 +01:00
David Shah
d5d9fb27a6 ice40: Validity check for LVDS IO 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 15:14:28 +01:00
David Shah
9834b68041 ice40: Remove obsolete belType member 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 14:27:50 +01:00
Eddie Hung
c9059fc7d0 [ice40] TimingPortClass of LC.O ports without any inputs now TMG_IGNORE 2018-09-15 15:16:21 -07:00
Clifford Wolf
801f630983 Add more missing iCE40 gfx (LP/HX is complete now) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 18:43:38 +02:00
Clifford Wolf
b7d4c7afd9 Add iCE40 gfx for IO span-4 corners 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 16:53:34 +02:00
Clifford Wolf
7cdafb8121 Add iCE40 gfx for span-4 wires between IO tiles 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 16:31:02 +02:00
Clifford Wolf
26be6f9761
Merge pull request #47 from YosysHQ/settings_propagate 
Use settings for placer1 and router1
 2018-08-18 19:25:19 +02:00
Clifford Wolf
456a83430a Improve iCE40 gfx for IO tiles and RAM tiles 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-18 16:20:33 +02:00
Clifford Wolf
5500cf3aff Add ice40 wire attributes (grid position, segment list) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-18 14:14:27 +02:00
Miodrag Milanovic
93a0d24560 Use settings for placer1 and router1 2018-08-09 18:39:10 +02:00
Clifford Wolf
f6189e4677 Merge branch 'master' of github.com:YosysHQ/nextpnr into constids 2018-08-08 19:35:13 +02:00
David Shah
751335977f ice40: Add error for unknown cell type when getting timing info 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 18:07:34 +02:00
Clifford Wolf
f875a37467 Get rid of old iCE40 id_ Arch members 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-08 17:17:16 +02:00
David Shah
433ad6462e Arch API: Removing Arch::isIOCell 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 17:06:59 +02:00
Clifford Wolf
e03ae50e21 Get rid of PortPin and BelType (ice40, generic, docs) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-08 17:01:18 +02:00
David Shah
e6eb203868 ice40: Add timing arcs through global buffers 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 16:34:41 +02:00
David Shah
d173ddba36 timing: Debugging implementation of new timing API 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 15:15:21 +02:00
David Shah
787fe5661c ice40: Timing arch fix 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 15:00:39 +02:00
David Shah
d8b3830031 timing: Update to new use API (currently broken) 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 14:58:43 +02:00
David Shah
bf42e525cb Arch API: New specification for timing port classes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 14:37:59 +02:00
Eddie Hung
f44a5fb904 clangformat 2018-08-06 17:35:23 -07:00
Eddie Hung
1b9a664bb1 Merge branch 'master' into assign_budget_speedup 2018-08-06 12:30:24 -07:00
Eddie Hung
9addcac09c ice40's getBudgetOverride() to return correct delay for different devices 2018-08-06 12:22:13 -07:00
Eddie Hung
21cd1d7dd6 Add new Arch::isIOCell() API function 2018-08-06 12:11:47 -07:00
Eddie Hung
0f3459dbe5 Fix ice40's getBudgetOverride() to override only for COUT -> CIN 2018-08-06 08:22:08 -07:00
Eddie Hung
823ceaacbf Change getBudgetOverride() signature to return bool and modify budget in place 2018-08-06 07:56:28 -07:00
Clifford Wolf
5e53075990 API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-05 15:25:42 +02:00
Clifford Wolf
287fe7e894 clangformat 2018-08-05 14:18:34 +02:00
Clifford Wolf
f6b3333a7d Add new iCE40 delay estimator and delay predictor 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 19:50:49 +02:00
Clifford Wolf
31fe52581b Add generation of models to tmfuzz 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 16:54:12 +02:00
Clifford Wolf
bd36cc1275 Refactor ice40 timing fuzzer used to create delay estimates 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 13:41:42 +02:00
Clifford Wolf
96291f17aa Merge branch 'master' of github.com:YosysHQ/nextpnr into lutperm 2018-08-04 10:32:07 +02:00
David Shah
082b8bf272 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-04 08:18:04 +02:00
Clifford Wolf
8d372b86f3 Proper ice40 wire types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-03 21:11:12 +02:00
David Shah
b937e6defe Add constraint weight as a command line option 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 18:31:54 +02:00
Clifford Wolf
2a1d54389f Add iCE40 pseudo-pips for lut permutation 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-03 17:37:59 +02:00
David Shah
a7269a685e ice40: Use real cell timings 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-02 16:02:51 +02:00
Clifford Wolf
6ccf8629b5 Add Router1Cfg 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-02 13:58:23 +02:00
Clifford Wolf
29dd98420b Remove getFrameDecal() API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-01 11:30:11 +02:00
Eddie Hung
92ec2cd138 clangformat for stuff I've touched 2018-07-31 20:57:36 -07:00
Eddie Hung
f646ec790a Modify the getNetinfo*() functions and getBudgetOverride() to not use 
user_idx and to take a PortRef& instead
 2018-07-31 19:31:54 -07:00
Eddie Hung
2d75053744 Merge remote-tracking branch 'origin/estdelay' into redist_slack 
Conflicts:
	ecp5/arch.cc
	generic/arch.cc
	ice40/arch.cc
 2018-07-31 16:18:08 -07:00
Eddie Hung
70747b9355 Merge branch 'redist_slack' into 'redist_slack' 
# Conflicts:
#   common/timing.cc
 2018-07-31 17:51:56 +00:00
Clifford Wolf
41726087b7 getChipName() should be const 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-31 17:01:38 +02:00
Clifford Wolf
32ff0059fe Add binary search to getBelPinWire() and getBelPinType() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-31 11:55:25 +02:00