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Author SHA1 Message Date
YRabbit
e6a8d0f4fc Merge branch 'master' into pll-pins 2022-12-04 21:33:36 +10:00
myrtle
db25c5c889
Merge pull request #1054 from YosysHQ/gatecat/api-add-const 
api: Make NetInfo* of checkPipAvailForNet const
 2022-12-04 12:27:53 +01:00
YRabbit
2e68962a02 gowin: add PLL pins processing 
Uses the information of the special input pins for the PLL in the
current chip. If such pins are involved, no routing is performed and
information about the use of implicit wires is passed to the packer.

The RESET and RESET_P inputs are now also disabled if they are connected
to VSS/VCC.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-12-04 15:06:44 +10:00
gatecat
91454515f4 Unbreak CI 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-02 14:26:13 +01:00
gatecat
c62a947a28 api: Make NetInfo* of checkPipAvailForNet const 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-02 14:20:39 +01:00
myrtle
f07d9a1835
Merge pull request #1048 from yrabbit/chipdb-cfg 
gowin: add information about pin configurations
 2022-12-02 09:58:46 +01:00
YRabbit
b0791a01c9 gowin: update the apicula version 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-12-02 08:49:56 +10:00
YRabbit
7638146782 Merge branch 'master' into chipdb-cfg 2022-12-02 08:28:51 +10:00
myrtle
719f89806a
Merge pull request #1053 from YosysHQ/gatecat/pbfix 
ecp5: Fix Python bindings for pip iterators
 2022-11-28 09:45:11 +01:00
gatecat
6ee3daf06a ecp5: Fix Python bindings for pip iterators 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-11-28 09:00:41 +01:00
YRabbit
ec53ae0c3b gowin: add information about pin configurations 
Includes information on additional pin functions such as RPLL_C_IN, GCLKC_3, SCLK and others.
This allows a decision to be made about special network routing of such pins

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-11-25 20:49:26 +10:00
myrtle
c61d490bd4
Merge pull request #1045 from yrabbit/unused-ports 
gowin: mark the PLL ports that are not in use
 2022-11-20 13:55:01 +01:00
YRabbit
378ca60a2f gowin: mark the PLL ports that are not in use 
Unused ports are deactivated by special fuse combinations, rather than
being left dangling in the air.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-11-20 22:04:09 +10:00
myrtle
c8406b71fe
Merge pull request #1042 from yrabbit/add-z1 
gowin: add support for a more common chip
 2022-11-12 11:17:06 +01:00
YRabbit
d4642d918c gowin: add support for a more common chip 
The GW1N-1 and GW1NZ-1 have a similar PLL, but the board with the former
chip is already very hard to buy, so let's experiment with a more
affordable chip.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-11-12 10:12:43 +10:00
myrtle
1aa9cda77a
Merge pull request #1040 from yrabbit/pll-stage0 
gowin: add initial PLL support
 2022-11-11 10:28:19 +01:00
YRabbit
9013b2de50 gowin: use ctx->idf() a bit 
Replacing snprintf() with ctx->idf() in PLL commit, but not yet a
complete overhaul.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-11-11 09:19:16 +10:00
myrtle
79cb2f9e20
Merge pull request #1041 from YosysHQ/gatecat/fix-copy-warning 
Fix "implicit copy constructor for 'Property' is deprecated"
 2022-11-10 15:40:50 +01:00
gatecat
8a69bd0735 Fix "implicit copy constructor for 'Property' is deprecated" 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-11-10 10:57:41 +01:00
gatecat
6930ab3acd fabulous: Tweak delay estimate 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-11-10 10:55:37 +01:00
YRabbit
a84ded4793 gowin: add initial PLL support 
The rPLL primitive for the simplest chip (GW1N-1) in the family is
processed. All parameters of the primitive are passed on to gowin_pack,
and general-purpose wires are used for routing outputs of the primitive.

Compatible with older versions of apicula, but in this case will refuse
to place the new primitive.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-11-10 19:14:41 +10:00
Miodrag Milanović
ac17c36bec
Merge pull request #1037 from YosysHQ/fix_python_ver 
Fix python version in CI
 2022-10-24 09:45:57 +02:00
Miodrag Milanovic
4ffa47d897 Fix python version in CI 2022-10-24 09:42:16 +02:00
Miodrag Milanovic
010b2e5ecf Update CI script 2022-10-24 09:28:34 +02:00
gatecat
445d32497d run clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-10-17 12:35:02 +02:00
myrtle
bd082132ce
Merge pull request #1034 from lushaylabs/support-windows-crlf 
Support windows line endings in constraints for nextpnr-gowin
 2022-10-17 12:33:33 +02:00
myrtle
c2dbaa2b11
Merge pull request #1035 from tyler274/patch-1 
Correct Not Equal operator implementation in ice40
 2022-10-17 10:43:34 +02:00
Tyler
613d84fb72
Correct Not Equal operator implementation in ice40 
I noticed this during my work reimplementing nextpnr, and it seems to be dead and wrong, or at least dead. Either way I think this is what was intended unless anyone can correct me.
 2022-10-17 01:19:51 -07:00
Lushay Labs
a7acda95f0
support windows line endings 2022-10-09 23:47:09 +03:00
myrtle
0d1ea9e6ed
Merge pull request #1032 from davidlattimore/registered-output-xform 
nexus: Transform registered output parameters
 2022-10-05 11:07:42 +02:00
David Lattimore
1602774d27 nexus: Transform registered output parameters 
Dual ported:
OUTREG_A -> OUT_REGMODE_A
OUTREG_B -> OUT_REGMODE_B

Pseudo dual ported:
OUTREG -> OUT_REGMODE_B

Single ported:
OUTREG -> OUT_REGMODE_A
 2022-10-05 14:40:49 +11:00
myrtle
41709dac8f
Merge pull request #1031 from YosysHQ/gatecat/fab-next 
fabulous: Add support for the CLB muxes
 2022-09-30 16:13:32 +02:00
gatecat
3826a31ad3 fabulous: Pack, validity check and FASM support for muxes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-30 13:27:51 +02:00
gatecat
124c0fc812 fabulous: Add split MUX bels 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-30 12:03:16 +02:00
myrtle
c44b034fc3
Merge pull request #1030 from YosysHQ/gatecat/ice40-dsp25_10-fix 
ice40: Fix handling of carry out route-thru via 25,14
 2022-09-26 11:48:48 +02:00
gatecat
a16d184956 ice40: Fix handling of carry out route-thru via 25,14 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-26 09:33:38 +02:00
myrtle
f0f9070adb
Merge pull request #1029 from airskywater/airskywater-patch-1 
Fix runtime segmentation fault
 2022-09-24 10:30:30 +02:00
airskywater
9572f6f032
Modify code to meet the code style preferences 2022-09-24 14:46:35 +08:00
airskywater
c702e15a3f
Add more sanity check for pointers 2022-09-24 12:03:44 +08:00
airskywater
78f67ae5bc
fix runtime segmentation fault 
disable null pointer dereference!
 2022-09-24 11:35:40 +08:00
myrtle
f4e6bbd383
Merge pull request #1019 from antmicro/support-clock-relations 
Support cross-domain clock relations in timing analyser
 2022-09-20 15:55:43 +02:00
Maciej Kurc
9000c41c4b Added the --ignore-rel-clk option to control timing checks for cross-domain paths, formatted code 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-09-20 14:40:40 +02:00
myrtle
136ab81cbd
Merge pull request #1028 from YosysHQ/gatecat/router2-reserve-src 
router2: Reserve source wire, too; ice40 fixes
 2022-09-20 14:37:55 +02:00
gatecat
a920ffcf70 ice40: implement checkPipAvailForNet 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-20 14:15:10 +02:00
gatecat
415c097df8 router2: Reserve source wire, too 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-20 13:42:51 +02:00
gatecat
376cedd558 fabulous: fix, but disable, IO configuration 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-16 09:32:15 +02:00
myrtle
a3a641f449
Merge pull request #1026 from YosysHQ/gatecat/ecp5-bitstream-refactor 
ecp5: Split bitstream generation into more functions
 2022-09-16 09:16:35 +02:00
myrtle
d58e85f297
Merge pull request #1023 from YosysHQ/gatecat/ice40up-bram-pol 
ice40: Fix UltraPlus BRAM clock polarity
 2022-09-16 06:38:04 +02:00
myrtle
e5da8be4f8
Merge pull request #1025 from YosysHQ/gatecat/nexus-dev-fixes 
nexus: Add ES2 device names and --list-devices
 2022-09-15 18:03:57 +02:00
gatecat
9e272810d8 ecp5: Split bitstream generation into more functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-15 13:28:43 +02:00