* Himbaechel Gowin: Add support for CLKDIV and CLKDIV2
* Himbaechel Gowin: Add support for CLKDIV and CLKDIV2
* Gowin Himbaechel: HCLK Bug fixes and corrections
DQCE and DCS primitives are added.
DQCE allows the internal logic to enable or disable the clock network in
the quadrant. When clock network is disabled, all logic drivern by this
clock is no longer toggled, thus reducing the total power consumtion of
the device.
DCS allows you to select one of four sources for two clock wires (6 and 7).
Wires 6 and 7 have not been used up to this point.
Since "hardware" primitives operate strictly in their own quadrants,
user-specified primitives are converted into one or more "hardware"
primitives as needed.
Also:
- minor edits to make the most of helper functions like connectPorts()
- when creating bases, the corresponding constants are assigned to the
VCC and GND wires, but for now huge nodes are used because, for an
unknown reason, the constants mechanism makes large examples
inoperable. So for now we remain on the nodes.
Compatible with older Apicula databases.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
As the board on the GW1N-1 chip becomes a rarity, its replacement is the
Tangnano1k board with the GW1NZ-1 chip. This chip has a unique mechanism
for turning off power to important things such as OSC, PLL, etc.
Here we introduce a primitive that allows energy saving to be controlled
dynamically.
We also bring the names of some functions to uniformity.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
In the images generated by Gowin IDE, the signals for dynamic BSRAM
block selection (BLKSEL[2:0]) are not always connected directly to the
ports - some chips add LUT2, LUT3 or LUT4 to turn these signals into
Clock Enable. Apparently there are chips with an error in the operation
of these ports.
Here we make such a decoder instead of using ports directly.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
It seems that the internal registers on the BSRAM output pins in
READ_MODE=1'b1 (pipeline) mode do not function properly because in the
images generated by Gowin IDE an external register is added to each pin,
and the BSRAM itself switches to READ_MODE=1'b0 (bypass) mode .
This is observed on Tangnano9k and Tangnano20k boards.
Here we repeat this fix.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Add description of BSRAM harness
In some cases, Gowin IDE adds a number of LUTs and DFFs to the BSRAM. Here we are trying to add similar elements.
More details with pictures: https://github.com/YosysHQ/apicula/blob/master/doc/bsram-fix.md
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
When multiplying 36 bits by 36 bits using four 18x18 multipliers, the
sign bits of the higher 18-bit parts of the multipliers were correctly
switched, but what was incorrect was leaving the sign bits of the lower
parts of the multipliers uninitialized. They now connect to VSS.
Addresses https://github.com/YosysHQ/apicula/issues/242
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
If the CLKIN input of the PLL is connected to a special pin, then it
makes sense to try to place the PLL so that it uses a direct implicit
non-switched connection to this pin.
The transfer of information about pins for various purposes has been
implemented (clock input signal, feedback, etc), but so far only CLKIN
is used.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
For the following primitives:
- PADD9
- PADD18
- MULT9X9
- MULT18X18
- MULT36X36
- MULTALU18X18
- MULTALU36X18
- MULTADDALU18X18
- ALU54D
packing and processing of fixed wires between macro and between DSP
blocks is implemented.
Clusters of DSP and macro blocks are processed using custom placement of
cluster elements.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Corrects the situation when it is impossible to use IOBUF with two
IOLOGIC elements at the same time - input and output.
Addresses https://github.com/YosysHQ/nextpnr/issues/1275
This is done by dividing one IOLOGIC Bel into two - input IOLOGIC and
output IOLOGIC plus checking for compatibility of the cells located
there.
At the moment, this check is simple and allows only the combination of
DDR and DDRC primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The OCE signal in the SP(X)9B primitive is intended to control the
built-in output register. The documentation states that this port is
invalid when READ_MODE=0 is used. However, it has been experimentally
established that you cannot simply apply VCC or GND to it and forget it
- the discrepancy between the signal on this port and the signal on the
CE port leads to both skipping data reading and unnecessary reading
after CE has switched to 0.
Here we force these ports to be connected to the network, except in the
case where the user controls the OCE signal using non-constant signals.
Also:
* All PIPs for clock spines are made inaccessible to the common router
- in general, using these routes for signals that have not been
processed by a special globals router is fraught with effects that
are difficult to detect.
* The INV primitive has been added purely to speed up development -
this primitive is not generated by Yosys, but is almost always
present in vendor output files.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The following primitives are implemented for the GW1NZ-1 chip:
* pROM - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9 - read only memory - (bitwidth: 9, 18, 36).
* SDPB - semidual port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B - semidual port - (bitwidth: 9, 18, 36).
* DPB - dual port - (bitwidth: 16).
* DPX9B - dual port - (bitwidth: 18).
* SP - single port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9 - single port - (bitwidth: 9, 18, 36).
Also:
- The creation of databases for GW1NS-2 has been removed - this was not
planned to be supported in Himbaechel from the very beginning and
even examples were not created in apicula for this chip due to the
lack of boards with it on sale.
- It is temporarily prohibited to connect DFFs and LUTs into clusters
because for some reason this prevents the creation of images on lower
chips (placer cannot find the placement), although without these
clusters the images are quite working. Requires further research.
- Added creation of ALU with mode 0 - addition. Such an element is not
generated by Yosys, but it is a favorite vendor element and its
support here greatly simplifies the compilation of vendor netlists.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Now the clock router can place a buffer into the specified network,
which divides the network into two parts: from the source to the buffer,
routing occurs through any available PIPs, and after the buffer to the
sink, only through a dedicated global clock network.
This is made specifically for the Tangnano20k where the external
oscillator is soldered to a regular non-clock pin. But it can be used
for other purposes, you just need to remember that the recipient must be
a CLK input or output pin.
The port/network to set the buffer to is specified in the .CST file:
CLOCK_LOC "name" BUFG;
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- experiment with notifyBelChange as an auxiliary cells reservation mechanism;
- since HCLK pips depend on the coordinates, and not on the tile type,
the tile type is copied if necessary;
- information about supported types of differential IO primitives has
been added to the extra information of the chip;
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
To implement unusual IOs that have a dynamically changing configuration
it is convenient to store the switching method in the additional chip
data.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- The global router is modified to work out the routing of PLL outputs and inputs;
- Added API function to change wire type after its creation - there was
a need to unify all wires included in the node at the stage of node
creation, when all wires have already been created.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Shamelessly adapted gatecat's router.
Very early version, not yet puzzled with recognizing clock sources and
controlling the type of wires involved.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- RAM16SDP1, RAM16SDP2 and RAM16SDP4 support;
- Reading in these primitives is asynchronous, but we have taken
measures so that DFF Bels remain unoccupied and they can be used
to implement synchronous reading.
- misc fixes.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- VSS and VCC sources in each cell are used;
- constant LUT inputs are disabled;
- putting the class declaration into a header file.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- wires, nodes and whites are generated from bases - apicula;
- roting of SN and EW bidirectional wires is supported;
- supports "wrapping" the wires at the edges of the chip;
- LUT1-4 and two types of DFF(R) are supported;
- simple IO is supported.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
