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Author SHA1 Message Date
Miodrag Milanovic
010b2e5ecf Update CI script 2022-10-24 09:28:34 +02:00
gatecat
445d32497d run clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-10-17 12:35:02 +02:00
myrtle
bd082132ce
Merge pull request #1034 from lushaylabs/support-windows-crlf 
Support windows line endings in constraints for nextpnr-gowin
 2022-10-17 12:33:33 +02:00
myrtle
c2dbaa2b11
Merge pull request #1035 from tyler274/patch-1 
Correct Not Equal operator implementation in ice40
 2022-10-17 10:43:34 +02:00
Tyler
613d84fb72
Correct Not Equal operator implementation in ice40 
I noticed this during my work reimplementing nextpnr, and it seems to be dead and wrong, or at least dead. Either way I think this is what was intended unless anyone can correct me.
 2022-10-17 01:19:51 -07:00
Lushay Labs
a7acda95f0
support windows line endings 2022-10-09 23:47:09 +03:00
myrtle
0d1ea9e6ed
Merge pull request #1032 from davidlattimore/registered-output-xform 
nexus: Transform registered output parameters
 2022-10-05 11:07:42 +02:00
David Lattimore
1602774d27 nexus: Transform registered output parameters 
Dual ported:
OUTREG_A -> OUT_REGMODE_A
OUTREG_B -> OUT_REGMODE_B

Pseudo dual ported:
OUTREG -> OUT_REGMODE_B

Single ported:
OUTREG -> OUT_REGMODE_A
 2022-10-05 14:40:49 +11:00
myrtle
41709dac8f
Merge pull request #1031 from YosysHQ/gatecat/fab-next 
fabulous: Add support for the CLB muxes
 2022-09-30 16:13:32 +02:00
gatecat
3826a31ad3 fabulous: Pack, validity check and FASM support for muxes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-30 13:27:51 +02:00
gatecat
124c0fc812 fabulous: Add split MUX bels 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-30 12:03:16 +02:00
myrtle
c44b034fc3
Merge pull request #1030 from YosysHQ/gatecat/ice40-dsp25_10-fix 
ice40: Fix handling of carry out route-thru via 25,14
 2022-09-26 11:48:48 +02:00
gatecat
a16d184956 ice40: Fix handling of carry out route-thru via 25,14 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-26 09:33:38 +02:00
myrtle
f0f9070adb
Merge pull request #1029 from airskywater/airskywater-patch-1 
Fix runtime segmentation fault
 2022-09-24 10:30:30 +02:00
airskywater
9572f6f032
Modify code to meet the code style preferences 2022-09-24 14:46:35 +08:00
airskywater
c702e15a3f
Add more sanity check for pointers 2022-09-24 12:03:44 +08:00
airskywater
78f67ae5bc
fix runtime segmentation fault 
disable null pointer dereference!
 2022-09-24 11:35:40 +08:00
myrtle
f4e6bbd383
Merge pull request #1019 from antmicro/support-clock-relations 
Support cross-domain clock relations in timing analyser
 2022-09-20 15:55:43 +02:00
Maciej Kurc
9000c41c4b Added the --ignore-rel-clk option to control timing checks for cross-domain paths, formatted code 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-09-20 14:40:40 +02:00
myrtle
136ab81cbd
Merge pull request #1028 from YosysHQ/gatecat/router2-reserve-src 
router2: Reserve source wire, too; ice40 fixes
 2022-09-20 14:37:55 +02:00
gatecat
a920ffcf70 ice40: implement checkPipAvailForNet 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-20 14:15:10 +02:00
gatecat
415c097df8 router2: Reserve source wire, too 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-20 13:42:51 +02:00
gatecat
376cedd558 fabulous: fix, but disable, IO configuration 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-16 09:32:15 +02:00
myrtle
a3a641f449
Merge pull request #1026 from YosysHQ/gatecat/ecp5-bitstream-refactor 
ecp5: Split bitstream generation into more functions
 2022-09-16 09:16:35 +02:00
myrtle
d58e85f297
Merge pull request #1023 from YosysHQ/gatecat/ice40up-bram-pol 
ice40: Fix UltraPlus BRAM clock polarity
 2022-09-16 06:38:04 +02:00
myrtle
e5da8be4f8
Merge pull request #1025 from YosysHQ/gatecat/nexus-dev-fixes 
nexus: Add ES2 device names and --list-devices
 2022-09-15 18:03:57 +02:00
gatecat
9e272810d8 ecp5: Split bitstream generation into more functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-15 13:28:43 +02:00
gatecat
7ca3ba3835 nexus: Add ES2 device names and --list-devices 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-15 12:27:36 +02:00
myrtle
79aad0988a
Merge pull request #1015 from YosysHQ/gatecat/fabulous-viaduct 
fabulous: Add a viaduct uarch
 2022-09-15 09:07:56 +02:00
myrtle
3983d4fe53
Merge pull request #1024 from YosysHQ/gatecat/pybind11-bump 
3rdparty: Bump vendored pybind11 version for py3.11 support
 2022-09-15 09:06:35 +02:00
gatecat
a72f898ff4 3rdparty: Bump vendored pybind11 version for py3.11 support 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-14 09:28:47 +02:00
gatecat
0a8c411692 ice40: Fix UltraPlus BRAM clock polarity 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-14 09:24:49 +02:00
gatecat
f423055390 fabulous: Add a viaduct uarch 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-09-09 14:48:57 +02:00
Maciej Kurc
1f1bae3e23 Code cleanup 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-08-31 16:19:15 +02:00
Maciej Kurc
60a6e8b070 Added timing check for cross-domain paths for related clocks 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-08-31 14:15:33 +02:00
Maciej Kurc
9a61ad9234 Augmented TimingAnalyser class with detection of clock to clock relations 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-08-30 17:30:58 +02:00
Maciej Kurc
8b6be09809 Fixed port timing classes of DCC ports in the Nexus architecture 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-08-30 17:30:13 +02:00
myrtle
f1349e114f
Merge pull request #1018 from yrabbit/bf-0 
gowin: BUGFIX. Really memorize the chip
 2022-08-25 11:14:50 +02:00
YRabbit
e0539f0ed7 gowin: BUGFIX. Really memorize the chip 
When it really needed to distinguish between the chips, this
unforgivable error was discovered :)

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-08-25 11:52:29 +10:00
myrtle
0f4166fedb
Merge pull request #1017 from YosysHQ/routerfix 
Router fix
 2022-08-22 13:31:11 +02:00
Miodrag Milanovic
a00b997cf1 add missing overrides 2022-08-22 12:35:24 +02:00
Miodrag Milanovic
1aa797b820 Fix parameter order 2022-08-22 12:32:50 +02:00
myrtle
ccf4367209
Merge pull request #1016 from atsampson/python3 
Use CMake's Python3 rather than PythonInterp in subdirs
 2022-08-21 20:53:10 +02:00
Adam Sampson
19160f10ae Use CMake's Python3 rather than PythonInterp in subdirs 2022-08-21 17:48:01 +01:00
gatecat
05167fcb8b pybindings: Mark CellInfo::bel as readonly 
bel bindings should be updated with bindBel/unbindBel during placement, or setting the BEL attribute for constraints before placement.

Fixes #522

Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-18 15:09:41 +02:00
myrtle
5c93d71c2a
Merge pull request #1014 from LAK132/master 
Replace deprecated method of finding Python 3
 2022-08-18 14:33:26 +02:00
LAK132
ae8966040b Replace deprecated method of finding Python 3 2022-08-17 01:07:14 +09:30
myrtle
b9b16eaa53
Merge pull request #1013 from YosysHQ/gatecat/viaduct-args 
viaduct: Allow passing command line options to uarch with -o
 2022-08-15 12:41:09 +02:00
gatecat
47da562600 viaduct: Allow passing command line options to uarch with -o 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-15 12:15:00 +02:00
myrtle
b653e39991
Merge pull request #1012 from YosysHQ/gatecat/refactor-id-in 
refactor: Use IdString::in instead of || chains
 2022-08-11 07:26:20 +01:00