Commit Graph

5 Commits

Author SHA1 Message Date
gatecat
523ffbaa37 interchange: Reserve site ports only reachable from dedicated routing
Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-01 11:28:12 +01:00
Alessandro Comodi
104536b7aa interchange: add support for generating BEL clusters
Clustering greatly helps the placer to identify and pack together
specific cells at the same site (e.g. LUT+FF), or cells that are chained through
dedicated interconnections (e.g. CARRY CHAINS)

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-06-11 11:19:01 +02:00
gatecat
ecc19c2c08 Using hashlib in arches
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:19 +01:00
Keith Rothman
831b94cdac Initial version of inverter logic.
For now just implements some inspection capabilities, and the site
router (for now) avoids inverted paths.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-23 09:03:07 -07:00
Keith Rothman
32f2ec86c4 Rework FPGA interchange site router.
The new site router should be robust to most situations, and isn't
significantly slower with the use of caching.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-22 09:54:49 -07:00