gatecat
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ef3be26a69
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Merge pull request #777 from YosysHQ/gatecat/gui-fixes
gui: Add about box and fix some small typos
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2021-07-25 13:07:47 +01:00 |
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gatecat
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bbb1ea26b6
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gui: Fix some typos
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-25 12:11:03 +01:00 |
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gatecat
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0e3b25468c
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gui: Implement about dialog
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-25 12:06:51 +01:00 |
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gatecat
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5212e38512
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Merge pull request #757 from antmicro/lut-mapping-cache
interchange: Add caching of site LUT mapping solution
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2021-07-22 14:09:40 +01:00 |
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Maciej Kurc
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580a45485a
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Added an option to disable the LUT mapping cache
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2021-07-22 14:07:35 +02:00 |
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Maciej Kurc
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8fc16a57c9
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Added more code comments, formatted the code
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2021-07-22 12:59:10 +02:00 |
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gatecat
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8733cce5fa
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Merge pull request #772 from antmicro/xdc_parse
[Interchange] Add dummy function to parse creat_clock in XDC files
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2021-07-21 18:53:15 +01:00 |
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Maciej Dudek
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0e838c3cea
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Add dummy function to parse creat_clock in XDC files
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
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2021-07-21 18:43:11 +02:00 |
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gatecat
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391248e031
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Merge pull request #768 from YosysHQ/gatecat/fix-gui-error
gui: Improve Fatal Error message
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2021-07-21 11:42:54 +01:00 |
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gatecat
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86a91ccf1b
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clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-21 10:57:48 +01:00 |
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gatecat
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1a5bb7b8ab
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Merge pull request #770 from YosysHQ/gatecat/empty-idstringlist
Fix definition of an empty IdStringList
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2021-07-20 18:25:49 +01:00 |
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gatecat
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ef08c4a91d
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Merge pull request #771 from YosysHQ/gatecat/ice40-ip-no-busaddr74
ice40: Use default value when IP is missing BUS_ADDR74 parameter
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2021-07-20 18:25:39 +01:00 |
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gatecat
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8f722a0d35
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ice40: Use default value when IP is missing BUS_ADDR74 parameter
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-20 16:08:26 +01:00 |
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gatecat
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08bbe173ce
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Fix definition of an empty IdStringList
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-20 15:51:04 +01:00 |
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gatecat
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41eecd7ce2
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gui: Improve Fatal Error message
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-20 15:01:34 +01:00 |
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gatecat
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f3be638ea9
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Merge pull request #767 from YosysHQ/gatecat/ic-pref-const
interchange: Fix preferred constant handling when canInvert
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2021-07-20 12:04:12 +01:00 |
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gatecat
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ffd97945ba
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interchange: Fix preferred constant handling when canInvert
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-20 10:42:04 +01:00 |
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gatecat
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c6aa51a2de
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Merge pull request #766 from pepijndevos/python
Remove python path from gowin target
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2021-07-17 20:37:04 +01:00 |
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Pepijn de Vos
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916ae180ac
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remove generic leftover in gowin
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2021-07-17 17:36:54 +02:00 |
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Pepijn de Vos
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811f5b4d18
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remove generic leftover in gowin
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2021-07-17 17:35:49 +02:00 |
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Maciej Kurc
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ccf2bb123c
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Added computing and reporting LUT mapping cache size
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2021-07-16 15:53:00 +02:00 |
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Maciej Kurc
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c95aa86a8e
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Fixed assertion typos
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2021-07-16 15:16:31 +02:00 |
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Maciej Kurc
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857961a6bb
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Migrated C arrays to std::array containers.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2021-07-16 14:55:45 +02:00 |
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Maciej Kurc
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0336f55b16
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LUT mapping ceche optimizations 2
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2021-07-16 13:55:19 +02:00 |
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Maciej Kurc
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044c9ba2d4
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LUT mapping cache optimizations 1
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2021-07-16 13:28:40 +02:00 |
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Maciej Kurc
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d52516756c
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Working site LUT mapping cache
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2021-07-16 12:51:28 +02:00 |
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gatecat
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2c4599612c
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Merge pull request #764 from acomodi/fix-pseudo-pips
interchange: disallow pseudo-pip on same nets if tile has luts
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2021-07-15 17:39:13 +01:00 |
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Alessandro Comodi
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7edfcc3bfa
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interchange: disallow pseudo-pip on same nets if tile has luts
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-07-15 16:06:00 +02:00 |
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gatecat
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084e15f9cf
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Merge pull request #762 from antmicro/testarch_timing
[interchange] Update chipdb and python-fpga-interchange versions
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2021-07-14 17:44:50 +01:00 |
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Maciej Dudek
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9190bda27d
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[interchange] Update chipdb and python-fpga-interchange versions
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
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2021-07-14 17:19:30 +02:00 |
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gatecat
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034467ff61
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Merge pull request #761 from acomodi/interchange-constrs
interchange: add user placement constraints handling
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2021-07-12 20:04:48 +01:00 |
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Alessandro Comodi
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7abfeb11c3
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interchange: xdc and place constr: address review comments
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-07-12 17:17:57 +02:00 |
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Alessandro Comodi
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3de0be7c06
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interchange: xdc: add get_cells command
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-07-12 16:45:11 +02:00 |
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Alessandro Comodi
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d9668df818
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interchange: add constraints constraints application routine
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-07-12 16:45:08 +02:00 |
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gatecat
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24b7084feb
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Merge pull request #760 from YosysHQ/gatecat/xcup-ibufds
interchange: Support for UltraScale+ differential input buffers
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2021-07-12 13:00:44 +01:00 |
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gatecat
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f03abe14d1
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interchange: Skip IO ports in dedicated routing check
These have already been dealt with in arch_pack_io
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-12 11:43:18 +01:00 |
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gatecat
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8604b03008
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interchange: Debug IO port validity check failures
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-12 11:40:23 +01:00 |
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gatecat
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96a5885051
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interchange: Place DIFFINBUF and IBUFCTRL for UltraScale+ IBUFDS
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-12 11:30:21 +01:00 |
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gatecat
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a63e7b3db8
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Merge pull request #759 from pepijndevos/gw1ndb
GW1NR is not a seperate family, but GW1NS is
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2021-07-11 14:00:52 +01:00 |
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Pepijn de Vos
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c89c14b6bf
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GW1NR is not a seperate family, but GW1NS is
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2021-07-11 14:12:34 +02:00 |
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gatecat
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eecc6147df
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Merge pull request #758 from YosysHQ/gatecat/hist-oob
timing: Fix out-of-bounds histogram bins in all cases
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2021-07-11 08:10:57 +01:00 |
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gatecat
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76070a7647
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timing: Fix out-of-bounds histogram bins in all cases
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-10 23:44:21 +01:00 |
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gatecat
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8531658019
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Merge branch 'master' of github.com:YosysHQ/nextpnr
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2021-07-10 23:24:38 +01:00 |
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gatecat
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d290766101
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ice40: Fix order of values in error
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-10 23:23:19 +01:00 |
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gatecat
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478456e6e9
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Merge pull request #755 from yrabbit/io_port
Pin modes parser
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2021-07-08 17:22:10 +01:00 |
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gatecat
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7b62c7fa50
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Merge pull request #756 from acomodi/fix-clustering-runtime
interchange: reduce run-time to check dedicated interconnect
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2021-07-08 16:58:44 +01:00 |
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Alessandro Comodi
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b64642fc99
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interchange: bump python-interchange version
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-07-08 16:51:23 +02:00 |
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Alessandro Comodi
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fbd291deaf
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interchange: update chipdb version
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-07-08 16:51:23 +02:00 |
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Alessandro Comodi
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dc0819b01a
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interchange: reduce run-time to check dedicated interconnect
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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2021-07-08 16:51:23 +02:00 |
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gatecat
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6829e4c197
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clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
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2021-07-08 15:42:36 +01:00 |
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