caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
4,582 Commits 22 Branches 7 Tags 17 MiB
f0325730a8
Commit Graph

201 Commits

Author SHA1 Message Date
Miodrag Milanovic
a00f810093 fix 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
6f85053b03 more like ecp5 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
3624fe90b2 one step closer 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
6508a0c267 This should not be here 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
153144022f More of making it inline 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
ca3d32e5ac make source more inline with ecp5 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
62ace58204 add missing bind and lutperm 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
7f8518d938 Import lutperm data 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
442142a47a typo fixes 2023-05-04 14:23:08 +02:00
Lofty
398b2ab569 bitstream emission update 2023-05-04 14:23:08 +02:00
Lofty
235a575267 port ecp5 split slice to machxo2 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
b033b915a6 Add bitgen for the rest of XO2 and XO3 2023-05-04 14:23:08 +02:00
Lofty
89c71bc8ac bitstream fixes for xo3 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
80705e9bbb Support enabling XO3 and XO3D 2023-05-04 14:23:08 +02:00
gatecat
6455b5dd26 viaduct: Add support for GUIs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-04-11 19:11:54 +02:00
Miodrag Milanovic
35eeaa7cc5 Add ramaining PIO tiles 2023-03-20 09:53:35 +01:00
Miodrag Milanovic
3f4c8d15d9 Use unified io location data 2023-03-20 09:53:35 +01:00
Miodrag Milanovic
0ce72e1a31 Use TRELLIS primitives 2023-03-20 09:53:35 +01:00
Miodrag Milanovic
ad5f6fccaa Use RelSlice, make more in line with ecp5 arch 2023-03-20 09:53:35 +01:00
gatecat
e4fcd3740d cmake: Make HeAP placer always-enabled 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-03-17 10:38:11 +01:00
gatecat
4111cc25d6 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-03-17 09:31:38 +01:00
Miodrag Milanovic
11a90aff83 Fix out of tree builds and place h in generated 2023-03-16 13:37:23 +01:00
Miodrag Milanovic
f008d7c4d8 Let top tiles be on top 2023-03-16 13:37:23 +01:00
Miodrag Milanovic
6eb5f2a77e Enable wires and add dummy wire type for now 2023-03-16 13:37:23 +01:00
Miodrag Milanovic
1f115ddd32 Basic GUI part selection 2023-03-16 13:37:23 +01:00
Miodrag Milanovic
26798038fe Fix examples 2023-03-16 13:37:23 +01:00
Miodrag Milanovic
7ad9914e51 Extend chipdb with metadata 2023-03-16 13:37:23 +01:00
Miodrag Milanovic
d5b5f7e4b2 add new field handling in chip config format 2023-03-16 13:37:23 +01:00
Miodrag Milanovic
4396a646a7 Add simple BEL graphics 2023-03-16 13:37:23 +01:00
Miodrag Milanovic
18ad718e53 Expand list of possible devices 2023-03-16 13:37:23 +01:00
Lofty
52b02f7377 machxo2: Fix Python bindings for pip iterators 2023-02-13 12:49:00 +00:00
gatecat
7845b66512 Add missing <set> includes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-01-20 09:04:41 +01:00
gatecat
603b60da8d api: add explain_invalid option to isBelLocationValid 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-07 10:27:58 +01:00
gatecat
e260ac33ab refactor: ArcBounds -> BoundingBox 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-12-07 10:00:53 +01:00
Adam Sampson
19160f10ae Use CMake's Python3 rather than PythonInterp in subdirs 2022-08-21 17:48:01 +01:00
gatecat
77c82b0fbf refactor: id(stringf(...)) to new idf(...) helper 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-10 10:57:46 +01:00
gatecat
86699b42f6 Switch to potentially-sparse net users array 
This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.

Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-27 13:47:05 +00:00
gatecat
6a32aca4ac refactor: New member functions to replace design_utils 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-18 11:13:18 +00:00
gatecat
76683a1e3c refactor: Use constids instead of id("..") 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-16 17:09:54 +00:00
gatecat
9ef0bc3d3a refactor: Use cell member functions to add ports 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-16 16:45:45 +00:00
gatecat
30fd86ce69 refactor: New NetInfo and CellInfo constructors 2022-02-16 15:10:57 +00:00
gatecat
ddb084e9a8 archapi: Use arbitrary rather than actual placement in predictDelay 
This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.

A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-19 17:15:15 +00:00
William D. Jones
064b6d808e clangformat. 2021-12-16 17:09:29 -05:00
William D. Jones
4d75792257 machxo2: Remove no-iobs option. It was always enabled and should remain an implementation detail. 2021-12-16 16:59:38 -05:00
William D. Jones
be3788fa30 machxo2: Remove -noiopad option when generating miters for post-pnr verification. 2021-12-16 16:59:38 -05:00
William D. Jones
365a871908 machxo2: Add packing logic to forbid designs lacking FACADE_IO top-level ports. 2021-12-16 16:59:38 -05:00
William D. Jones
d2ac6dffbc machxo2: Correct which PIO wires get adjusted when writing text bitstream. Add verbose logging for adjustments. 2021-12-16 16:59:37 -05:00
William D. Jones
41d09f7187 machxo2: Fix packing for directly-connected DFFs. 2021-07-01 09:59:53 -04:00
William D. Jones
e625876949 machxo2: Add VHDL primitives, demo, and script. 2021-07-01 09:36:03 -04:00
William D. Jones
45c33e9dcf machxo2: Add a special case for pips whose config bits are in multiple 
tiles.
 2021-07-01 09:36:02 -04:00
William D. Jones
ec239c8c35 machxo2: Hardcode a rule for emitting U_/D_ or G_ prefixes in ASCII output. 2021-07-01 09:36:01 -04:00
William D. Jones
b1f25d4b33 machxo2: Set Pip and Wire delays to reasonable fake values mirroring 
estimateDelay.
 2021-07-01 09:36:00 -04:00
gatecat
2ffb081442 Fixing old emails and names in copyrights 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:22:38 +01:00
gatecat
dcbb322447 Remove redundant code after hashlib move 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat
eca1a4cee4 Use hashlib in most remaining code 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat
ecc19c2c08 Using hashlib in arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:19 +01:00
gatecat
579b98c596 Use hashlib for core netlist structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
ff72454f83 Add hash() member functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
0d6be6f474 Add stub cluster API impl for remaining arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 13:12:52 +01:00
Miodrag Milanovic
157cc1b60c Add same fix as in issue #373 2021-04-08 12:33:34 +02:00
Keith Rothman
fe4608386e Split nextpnr.h to allow for linear inclusion. 
"nextpnr.h" is no longer the god header.  Important improvements:

 - Functions in log.h can be used without including
   BaseCtx/Arch/Context. This means that log_X functions can be called
   without included "nextpnr.h"

 - NPNR_ASSERT can be used without including "nextpnr.h" by including
   "nextpnr_assertions.h".  This allows NPNR_ASSERT to be used safely in
   any header file.

 - Types defined in "archdefs.h" are now available without including
   BaseCtx/Arch/Context.  This means that utility classes that will be
   used inside of BaseCtx/Arch/Context can be defined safely in a
   self-contained header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-15 09:05:23 -07:00
gatecat
23413a4d12 Fix compiler warnings introduced by -Wextra 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-25 15:15:25 +00:00
gatecat
7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad 
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 11:31:33 +00:00
gatecat
c7c13cd95f Remove isValidBelForCell 
This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.

In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).

Longer term, removing this API makes things a bit cleaner for a new
validity checking API.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-16 13:31:36 +00:00
gatecat
6de733b38c machxo2: Misc tidying up 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:43:15 +00:00
gatecat
33eca9a3d2 machxo2: Python bindings and stub GUI 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:40:03 +00:00
gatecat
8f5133d811 machxo2: Use snake_case for non-ArchAPI functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:36:59 +00:00
gatecat
b539363cd0 machxo2: Use IdStringLists in earnest 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:36:59 +00:00
gatecat
3f7618283d machxo2: Update with Arch API changes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:36:59 +00:00
William D. Jones
32433db7ae machxo2: Prepare README.md for first PR. 2021-02-12 10:36:59 +00:00
William D. Jones
3dbd5b0932 machxo2: Add prefix parameter to simtest.sh. Remove show command from 
simtest.sh. Update README.md.
 2021-02-12 10:36:59 +00:00
William D. Jones
730e543ca6 machxo2: Add prefix parameter to simple.sh. Update README.md. 2021-02-12 10:36:59 +00:00
William D. Jones
0b0faa2f1c machxo2: Fill in more about mitertest.sh in README.md and clean up a bit. 2021-02-12 10:36:59 +00:00
William D. Jones
73c851d8e0 machxo2: Add two new examples: blinky_ext and aforementioned UART. 2021-02-12 10:36:59 +00:00
William D. Jones
74b5e846a5 machxo2: auto-top does not work for smt miter either. 2021-02-12 10:36:59 +00:00
William D. Jones
77bb3e73cd machxo2: Fix unhelpful comment in mitertest.sh. 2021-02-12 10:36:59 +00:00
William D. Jones
2b54e87548 machxo2: Verilog examples using OSCH cannot be simulated in mitertest.sh. Remove show from mitertest.sh. 2021-02-12 10:36:59 +00:00
William D. Jones
a3a38b0536 machxo2: Add prefix parameter to mitertest.sh. All Verilog files top modules named "top". 2021-02-12 10:36:59 +00:00
William D. Jones
0aa472fb3a machxo2: Add prefix paramter to demo.sh. 2021-02-12 10:36:59 +00:00
mtnrbq
b9eb443e54 Add demo with RGB LED 2021-02-12 10:36:59 +00:00
William D. Jones
4948e8d914 machxo2: Fix packing when FF is driven by a constant; UART test core working on silicon, fails post-synth sim. 2021-02-12 10:36:59 +00:00
William D. Jones
086bca18b8 machxo2: Add packing logic to handle FFs fed with constant value; UART test core routes. 2021-02-12 10:36:59 +00:00
William D. Jones
3ab300a28e machxo2: Add additional packing phase to pack remaining FFs. 2021-02-12 10:36:59 +00:00
William D. Jones
f18df5ed59 machxo2: Don't write out config bits for cells without location info. 2021-02-12 10:36:59 +00:00
William D. Jones
da1b15d6f5 machxo2: Special-case left and right I/O wire names in ASCII generation. 2021-02-12 10:36:59 +00:00
William D. Jones
8629d7b692 machxo2: Add quickstart README.md. 2021-02-12 10:36:59 +00:00
William D. Jones
07bc6bac53 machxo2: Fail CMake configuration is BUILD_PYTHON is ON (not supported for now). 2021-02-12 10:36:59 +00:00
William D. Jones
c9487293e9 machxo2: Fix REGMODE identifier (per slice, not per-FF). 2021-02-12 10:36:59 +00:00
William D. Jones
d0b822c036 machxo2: Add demo.sh TinyFPGA Ax example. 2021-02-12 10:36:59 +00:00
William D. Jones
0250aaaddd machxo2: clang format. 2021-02-12 10:36:59 +00:00
William D. Jones
2c9d4ba9ae machxo2: Fix reversed interpretation of REG_SD config bits. 2021-02-12 10:36:59 +00:00
William D. Jones
0d00c10e2f machxo2: Add bitstream generation for OSCH. 2021-02-12 10:36:59 +00:00
William D. Jones
884e7d9a98 machxo2: Add basic bitstream generation for PIC tiles and I/O. 2021-02-12 10:36:59 +00:00
William D. Jones
d485dc6ef6 machxo2: Add REGMODE to bitstream output. 2021-02-12 10:36:59 +00:00
William D. Jones
5415194b39 machxo2: Checkpoint commit for slice bitstream generation. 2021-02-12 10:36:59 +00:00
William D. Jones
cf2db7a4c4 machxo2: Write out pips to bitstream. 2021-02-12 10:36:59 +00:00
William D. Jones
56656b2b24 machxo2: Emit empty bitstream file. 2021-02-12 10:36:59 +00:00
William D. Jones
695fb7e569 machxo2: Add/fix copyright banners. 2021-02-12 10:36:59 +00:00
William D. Jones
75f33e0c55 machxo2: Add stub bitstream writer plus support files. 2021-02-12 10:36:59 +00:00
William D. Jones
e1f72318e0 machxo2: Tweak A-star parameters for acceptable performance. 2021-02-12 10:36:59 +00:00