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201 Commits

Author SHA1 Message Date
William D. Jones
ec239c8c35 machxo2: Hardcode a rule for emitting U_/D_ or G_ prefixes in ASCII output. 2021-07-01 09:36:01 -04:00
William D. Jones
b1f25d4b33 machxo2: Set Pip and Wire delays to reasonable fake values mirroring 
estimateDelay.
 2021-07-01 09:36:00 -04:00
gatecat
2ffb081442 Fixing old emails and names in copyrights 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:22:38 +01:00
gatecat
dcbb322447 Remove redundant code after hashlib move 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat
eca1a4cee4 Use hashlib in most remaining code 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat
ecc19c2c08 Using hashlib in arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:19 +01:00
gatecat
579b98c596 Use hashlib for core netlist structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
ff72454f83 Add hash() member functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
0d6be6f474 Add stub cluster API impl for remaining arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 13:12:52 +01:00
Miodrag Milanovic
157cc1b60c Add same fix as in issue #373 2021-04-08 12:33:34 +02:00
Keith Rothman
fe4608386e Split nextpnr.h to allow for linear inclusion. 
"nextpnr.h" is no longer the god header.  Important improvements:

 - Functions in log.h can be used without including
   BaseCtx/Arch/Context. This means that log_X functions can be called
   without included "nextpnr.h"

 - NPNR_ASSERT can be used without including "nextpnr.h" by including
   "nextpnr_assertions.h".  This allows NPNR_ASSERT to be used safely in
   any header file.

 - Types defined in "archdefs.h" are now available without including
   BaseCtx/Arch/Context.  This means that utility classes that will be
   used inside of BaseCtx/Arch/Context can be defined safely in a
   self-contained header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-15 09:05:23 -07:00
gatecat
23413a4d12 Fix compiler warnings introduced by -Wextra 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-25 15:15:25 +00:00
gatecat
7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad 
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 11:31:33 +00:00
gatecat
c7c13cd95f Remove isValidBelForCell 
This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.

In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).

Longer term, removing this API makes things a bit cleaner for a new
validity checking API.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-16 13:31:36 +00:00
gatecat
6de733b38c machxo2: Misc tidying up 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:43:15 +00:00
gatecat
33eca9a3d2 machxo2: Python bindings and stub GUI 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:40:03 +00:00
gatecat
8f5133d811 machxo2: Use snake_case for non-ArchAPI functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:36:59 +00:00
gatecat
b539363cd0 machxo2: Use IdStringLists in earnest 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:36:59 +00:00
gatecat
3f7618283d machxo2: Update with Arch API changes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:36:59 +00:00
William D. Jones
32433db7ae machxo2: Prepare README.md for first PR. 2021-02-12 10:36:59 +00:00
William D. Jones
3dbd5b0932 machxo2: Add prefix parameter to simtest.sh. Remove show command from 
simtest.sh. Update README.md.
 2021-02-12 10:36:59 +00:00
William D. Jones
730e543ca6 machxo2: Add prefix parameter to simple.sh. Update README.md. 2021-02-12 10:36:59 +00:00
William D. Jones
0b0faa2f1c machxo2: Fill in more about mitertest.sh in README.md and clean up a bit. 2021-02-12 10:36:59 +00:00
William D. Jones
73c851d8e0 machxo2: Add two new examples: blinky_ext and aforementioned UART. 2021-02-12 10:36:59 +00:00
William D. Jones
74b5e846a5 machxo2: auto-top does not work for smt miter either. 2021-02-12 10:36:59 +00:00
William D. Jones
77bb3e73cd machxo2: Fix unhelpful comment in mitertest.sh. 2021-02-12 10:36:59 +00:00
William D. Jones
2b54e87548 machxo2: Verilog examples using OSCH cannot be simulated in mitertest.sh. Remove show from mitertest.sh. 2021-02-12 10:36:59 +00:00
William D. Jones
a3a38b0536 machxo2: Add prefix parameter to mitertest.sh. All Verilog files top modules named "top". 2021-02-12 10:36:59 +00:00
William D. Jones
0aa472fb3a machxo2: Add prefix paramter to demo.sh. 2021-02-12 10:36:59 +00:00
mtnrbq
b9eb443e54 Add demo with RGB LED 2021-02-12 10:36:59 +00:00
William D. Jones
4948e8d914 machxo2: Fix packing when FF is driven by a constant; UART test core working on silicon, fails post-synth sim. 2021-02-12 10:36:59 +00:00
William D. Jones
086bca18b8 machxo2: Add packing logic to handle FFs fed with constant value; UART test core routes. 2021-02-12 10:36:59 +00:00
William D. Jones
3ab300a28e machxo2: Add additional packing phase to pack remaining FFs. 2021-02-12 10:36:59 +00:00
William D. Jones
f18df5ed59 machxo2: Don't write out config bits for cells without location info. 2021-02-12 10:36:59 +00:00
William D. Jones
da1b15d6f5 machxo2: Special-case left and right I/O wire names in ASCII generation. 2021-02-12 10:36:59 +00:00
William D. Jones
8629d7b692 machxo2: Add quickstart README.md. 2021-02-12 10:36:59 +00:00
William D. Jones
07bc6bac53 machxo2: Fail CMake configuration is BUILD_PYTHON is ON (not supported for now). 2021-02-12 10:36:59 +00:00
William D. Jones
c9487293e9 machxo2: Fix REGMODE identifier (per slice, not per-FF). 2021-02-12 10:36:59 +00:00
William D. Jones
d0b822c036 machxo2: Add demo.sh TinyFPGA Ax example. 2021-02-12 10:36:59 +00:00
William D. Jones
0250aaaddd machxo2: clang format. 2021-02-12 10:36:59 +00:00
William D. Jones
2c9d4ba9ae machxo2: Fix reversed interpretation of REG_SD config bits. 2021-02-12 10:36:59 +00:00
William D. Jones
0d00c10e2f machxo2: Add bitstream generation for OSCH. 2021-02-12 10:36:59 +00:00
William D. Jones
884e7d9a98 machxo2: Add basic bitstream generation for PIC tiles and I/O. 2021-02-12 10:36:59 +00:00
William D. Jones
d485dc6ef6 machxo2: Add REGMODE to bitstream output. 2021-02-12 10:36:59 +00:00
William D. Jones
5415194b39 machxo2: Checkpoint commit for slice bitstream generation. 2021-02-12 10:36:59 +00:00
William D. Jones
cf2db7a4c4 machxo2: Write out pips to bitstream. 2021-02-12 10:36:59 +00:00
William D. Jones
56656b2b24 machxo2: Emit empty bitstream file. 2021-02-12 10:36:59 +00:00
William D. Jones
695fb7e569 machxo2: Add/fix copyright banners. 2021-02-12 10:36:59 +00:00
William D. Jones
75f33e0c55 machxo2: Add stub bitstream writer plus support files. 2021-02-12 10:36:59 +00:00
William D. Jones
e1f72318e0 machxo2: Tweak A-star parameters for acceptable performance. 2021-02-12 10:36:59 +00:00
William D. Jones
447b3a060c machxo2: Fix getWireName. 2021-02-12 10:36:59 +00:00
William D. Jones
385917059b machxo2: Fix typos where absolute positions were treated as relative. 2021-02-12 10:36:59 +00:00
William D. Jones
722d1f2542 machxo2: Finish implementing Wire API functions. nextpnr segfaults on example with constraints. 2021-02-12 10:36:59 +00:00
William D. Jones
861c12e6eb machxo2: Finish implementing Pip API functions. 2021-02-12 10:36:59 +00:00
William D. Jones
0adde4aede machxo2: Implement 4 more Wire/Pip API functions. 2021-02-12 10:36:59 +00:00
William D. Jones
19a9554bda machxo2: Add stub getAttrs API functions. 2021-02-12 10:36:59 +00:00
William D. Jones
9a9054188c machxo2: Implement getByName/getName for Wires and Pips. 2021-02-12 10:36:59 +00:00
William D. Jones
e4a6fd3571 machxo2: Convert facade_import to use pybind API from pytrellis. 2021-02-12 10:36:59 +00:00
William D. Jones
31ea8f8719 machxo2: Use attrmvcp in yosys to implement LOC constraint and only check for LOC on FACADE_IO. 2021-02-12 10:36:59 +00:00
William D. Jones
9c37aef499 machxo2: Detect LOC attributes during packing to implement rudimentary user constraints. 2021-02-12 10:36:59 +00:00
William D. Jones
0e63178fe1 machxo2: clang format. 2021-02-12 10:36:59 +00:00
William D. Jones
91ad064249 machxo2: Import remaining iterators from ECP5. 2021-02-12 10:36:59 +00:00
William D. Jones
a7917c9c63 machxo2: Implement WireId/PipId, complete Bel part of API. 2021-02-12 10:36:59 +00:00
William D. Jones
bbc683dd75 machxo2: Implement all of Bel API except getBelPinWire. 2021-02-12 10:36:59 +00:00
William D. Jones
138519d820 machxo2: Fix place phase segfault. Placement suceeds with warning of no clock. 2021-02-12 10:36:59 +00:00
William D. Jones
8a94a3451f machxo2: Stub valid BEL functions with comment. Place phase segfaults. 2021-02-12 10:36:59 +00:00
William D. Jones
5f748272fc machxo2: Implement bel_to_cell and API functions using it. 2021-02-12 10:36:59 +00:00
William D. Jones
682de724a8 machxo2: Implement 2 Bel API functions. 2021-02-12 10:36:59 +00:00
William D. Jones
3e6be4bbfd machxo2: Implement General Methods. 2021-02-12 10:36:59 +00:00
William D. Jones
094233a4ab machxo2: Implement getBelLocation to stop std::out_of_range in place phase. 2021-02-12 10:36:59 +00:00
William D. Jones
52b424c385 machxo2: Convert uint_t to int_t in packed structs. 2021-02-12 10:36:59 +00:00
William D. Jones
dc07054ee8 machxo2: Implement functions to get device utilization (throws std::out_of_range during place phase). 2021-02-12 10:36:59 +00:00
William D. Jones
ec4a9685ab machxo2: Initialize Arch context with device type and package. 2021-02-12 10:36:59 +00:00
William D. Jones
6f6aaa4a97 machxo2: Add binary blob struct definitions. 2021-02-12 10:36:59 +00:00
William D. Jones
a3a3a91b72 machxo2: Clean up packing pass a bit. 2021-02-12 10:36:59 +00:00
William D. Jones
c5292e0db5 machxo2: Finalize (hopefully) facade_import for prototype. 2021-02-12 10:36:59 +00:00
William D. Jones
3d287adbcf machxo2: Add package/IO info to facade_import. 2021-02-12 10:36:59 +00:00
William D. Jones
b739513894 machxo2: Import constids and BELs into facade_import. 2021-02-12 10:36:59 +00:00
William D. Jones
dfedef5772 machxo2: Add pip and wire info into facade_import. 2021-02-12 10:36:59 +00:00
William D. Jones
e0b14ba98e machxo2: Begin populating binary blob via facade_import. 2021-02-12 10:36:59 +00:00
William D. Jones
6ce2edc2f1 machxo2: Add SMT mode to mitertest.sh 2021-02-12 10:36:59 +00:00
William D. Jones
4f042eac53 machxo2: Rework examples to test pack, place, and route phases. 2021-02-12 10:36:59 +00:00
William D. Jones
5838662b2f machxo2: Make sure REGSET FF parameter is set in FACADE_SLICE. Init blinky ctr to 0 for miter circuit. 2021-02-12 10:36:59 +00:00
William D. Jones
da6204442f machxo2: Add LUT and FF packing functions. 2021-02-12 10:36:59 +00:00
William D. Jones
f2a240550e machxo2: Always remove nextpnr_iobufs for now- assume manually instantiated primitives. 2021-02-12 10:36:59 +00:00
William D. Jones
42214b226f machxo2: Add constant packing implementation, fix bugs in create_machxo2_cell. 2021-02-12 10:36:59 +00:00
William D. Jones
3424badeff machxo2: Create basic cells for packing. 2021-02-12 10:36:59 +00:00
William D. Jones
5c30f95c42 machxo2: Add initial set of constids for packing. 2021-02-12 10:36:59 +00:00
William D. Jones
1cde40792f machxo2: Improve examples directory. 2021-02-12 10:36:59 +00:00
William D. Jones
ade94efbff machxo2: synth directory (simulation, techmaps, synth script) is now provided by yosys. 2021-02-12 10:36:59 +00:00
William D. Jones
59efba2fc0 machxo2: Stub out cells functions. 2021-02-12 10:36:59 +00:00
William D. Jones
88b7dfce58 machxo2: Stub out arch API functions and members. 2021-02-12 10:36:59 +00:00
William D. Jones
e5576448ea machxo2: Remove HeAP placer for now, fix typos. 2021-02-12 10:36:59 +00:00
William D. Jones
512daf2c89 machxo2: Remove generic packing. 2021-02-12 10:36:59 +00:00
William D. Jones
9704f422dc machxo2: Start creating MachXO2CommandHandler. 2021-02-12 10:36:59 +00:00
William D. Jones
98214865be machxo2: Remove generic API functions from Arch. 2021-02-12 10:36:59 +00:00
William D. Jones
78880e1fdf machxo2: Remove pybindings unneeded files from examples and update README.md and scripts accordingly. Delete resources directory. 2021-02-12 10:36:59 +00:00
William D. Jones
539651609c Update machxo2 backend with minimal build system changes so nextpnr compiles again. 2021-02-12 10:36:59 +00:00
William D. Jones
c38762f91f Update machxo2 backend with build system changes. 2021-02-12 10:36:59 +00:00
William D. Jones
81d6bc3614 Create sub import of facade DB for 1200 device. 
Signed-off-by: William D. Jones <thor0505@comcast.net>
 2021-02-12 10:36:59 +00:00
gatecat
510969ab97 Create machxo2 backend (renamed from generic). 
Signed-off-by: William D. Jones <thor0505@comcast.net>
 2021-02-12 10:36:59 +00:00