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90 Commits

Author SHA1 Message Date
Clifford Wolf
f6b3333a7d Add new iCE40 delay estimator and delay predictor 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 19:50:49 +02:00
Clifford Wolf
700e68746a Fix bug in ice40 chipdby.py add_wire() that moves some wires to X0/Y0 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 13:33:24 +02:00
Clifford Wolf
96291f17aa Merge branch 'master' of github.com:YosysHQ/nextpnr into lutperm 2018-08-04 10:32:07 +02:00
David Shah
affc6da1af ice40: Add SB_GB timing to database 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-04 08:28:13 +02:00
Clifford Wolf
8d372b86f3 Proper ice40 wire types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-03 21:11:12 +02:00
Clifford Wolf
2a1d54389f Add iCE40 pseudo-pips for lut permutation 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-03 17:37:59 +02:00
Clifford Wolf
e673d9d2db
Merge pull request #22 from YosysHQ/routethru 
Add iCE40 LUT route-through pips
 2018-08-03 12:51:37 +02:00
Clifford Wolf
36009645ce Add LUT route-through pips to iCE40 architecture database 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-02 16:28:47 +02:00
David Shah
a7269a685e ice40: Use real cell timings 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-02 16:02:51 +02:00
David Shah
c0aaac8dfa ice40: Adding cell timings to chipdb 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-02 15:20:43 +02:00
Clifford Wolf
2652485a01 Use icestorm timing information 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-31 16:43:19 +02:00
Clifford Wolf
32ff0059fe Add binary search to getBelPinWire() and getBelPinType() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-31 11:55:25 +02:00
Clifford Wolf
b121008372 Towards better ice40 timing data 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-30 17:17:07 +02:00
David Shah
84e0082925 cmake: Set --fast and --slow chipdb.py arguments 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-30 16:40:56 +02:00
Clifford Wolf
3d8b0087c3 Add ice40 chipdb.py --fast/--slow 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-30 16:36:34 +02:00
Clifford Wolf
8f9b031ef0 Add iCE40 fast/slow delay fields to chipdb 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-30 16:21:20 +02:00
Clifford Wolf
a86c4f2f5d Improvements in bbasm 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-26 15:22:52 +02:00
Clifford Wolf
c3859072d4 Use bbasm to create iCE40 chipdb 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-24 21:10:42 +02:00
Sergiusz Bazanski
b31e95f82c Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/pll 2018-07-24 15:54:03 +01:00
Clifford Wolf
c0c8dc7602 Remove uphill/downhill bel pins from ice40 db 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-24 15:44:39 +02:00
David Shah
a09f95bb06 ice40: Fix SPRAM and other primitives in corners other than (0, 0) 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-24 11:16:33 +02:00
Sergiusz Bazanski
eaae1d299c ice40: move PLL->IO from pseudo pip to second uphill bel 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
65ceb20784 ice40: emit list of upbels in chipdb 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
69233385f8 ice40: Emit feed-through LUTs for PLL/LOCK 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
2b1f7875bb ice40: Implement emitting PLLs 2018-07-24 02:38:10 +01:00
Clifford Wolf
e647604e2a Add Context::archcheck() and "nextpnr-ice40 --test" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-23 14:03:23 +02:00
Clifford Wolf
3788bd26e6 Bugfix in iCE40 chipdb.py 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-23 00:25:49 +02:00
Clifford Wolf
b60c9485d2 Add Arch::getBelPinType() and Arch::getWireBelPins() in iCE40 arch 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 11:56:51 +02:00
David Shah
0cb9ec0757 ice40: Add virtual padin wires for intoscs and GB_IOs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-19 12:04:35 +02:00
David Shah
b0d9b994eb ice40: Adding data for extra cell configuration 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-19 11:14:43 +02:00
Clifford Wolf
5531546d6b Remove pip names from ice40 chip db to safe memory 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-15 21:41:34 +02:00
Clifford Wolf
164bd28348 Add iCE40 Pip gfx 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-15 20:29:32 +02:00
Clifford Wolf
44663fa589 Fix ice40 gfx wire indices 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-13 15:44:39 +02:00
Clifford Wolf
b8a42ff53b Updates from clang-format 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-12 22:04:13 +02:00
Clifford Wolf
ad60ab2ef1 Fix ice40 wire segments in lutff complex 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-12 21:46:16 +02:00
Clifford Wolf
4f87ea0eb6 Improve iCE40 wire database and gfx 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-12 21:05:09 +02:00
Clifford Wolf
6ffae27aa1 Deterministic chipdb blobs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-11 18:36:15 +02:00
Miodrag Milanovic
fd3c124f87 Add opetion to defie ICEBOX_ROOT, fix compile on other location 2018-07-03 20:46:05 +02:00
Miodrag Milanovic
ec9a9de6d3 Make chibdb.py able to generate pure binary output 2018-07-03 20:14:49 +02:00
David Shah
6a783ef94f Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr 2018-06-22 18:35:18 +02:00
David Shah
60e885d342 ice40: Adding extra cell wires to database; SB_WARMBOOT working 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-22 18:35:08 +02:00
Serge Bazanski
5dfe1969af Merge branch 'q3k/gl' into 'master' 
Modern OpenGL renderer

See merge request SymbioticEDA/nextpnr!1
 2018-06-22 16:17:21 +00:00
David Shah
7c169c48d0 ice40: Preparations for extra cells support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-22 17:44:26 +02:00
Sergiusz Bazanski
15a7a76415 Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/gl 2018-06-22 15:54:05 +01:00
David Shah
cf78f1b0e4 ice40: Add UltraPlus tiles to database 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-22 16:40:22 +02:00
Sergiusz Bazanski
4e480a9a61 chipdb.py style fix 2018-06-20 20:28:48 +01:00
Clifford Wolf
9475997a2d Improve --tmfuzz mode and iCE40 delay estimator 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-20 19:22:03 +02:00
David Shah
d5a032d00e Fix chipdb UltraPlus wires 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-20 13:10:40 +02:00
Clifford Wolf
c3837027b2 Add better iCE40 delay estimates 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-20 12:50:38 +02:00
Clifford Wolf
acfef6971e Refactore ice40 chipdb to use a super-large C-string as output format 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-17 18:15:41 +02:00