David Shah
|
f07bd98d59
|
ecp5: Better use of Boost
Signed-off-by: David Shah <dave@ds0.me>
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2018-11-16 09:58:18 +00:00 |
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David Shah
|
7e1df82462
|
ecp5: Regression fix & format
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:54:28 +00:00 |
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David Shah
|
91a0927196
|
ecp5: Support LOC attribute on DCUs
Signed-off-by: David Shah <dave@ds0.me>
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2018-11-15 11:30:27 +00:00 |
|
David Shah
|
01e0da16f0
|
ecp5: Add DCU availability check
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:30:27 +00:00 |
|
David Shah
|
02736d0680
|
ecp5: Add timing info for SERDES
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:30:27 +00:00 |
|
David Shah
|
084f9cf63f
|
ecp5: DCU clocking fixes
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:30:27 +00:00 |
|
David Shah
|
0eba7d9789
|
ecp5: EXTREFB fixes
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:30:27 +00:00 |
|
David Shah
|
bc022173f0
|
ecp5: clangformat
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:30:27 +00:00 |
|
David Shah
|
36178a5713
|
ecp5: Trim IO connected to top level ports
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:30:27 +00:00 |
|
David Shah
|
e9fe444dc7
|
ecp5: Adding ancillary DCU bels
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:30:27 +00:00 |
|
David Shah
|
37cbabecfb
|
ecp5: remove debug and clangformat
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:30:27 +00:00 |
|
David Shah
|
c9d83ec08b
|
dcu: Fix bitstream param handling
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:30:27 +00:00 |
|
David Shah
|
4f8dfd8e1b
|
ecp5: Prefer DCCs with dedicated routing when placing DCCs
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:30:27 +00:00 |
|
David Shah
|
c5a3571a06
|
ecp5: Working on DCU
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:30:27 +00:00 |
|
David Shah
|
983903887d
|
ecp5: DCU bitstream gen handling
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:30:27 +00:00 |
|
David Shah
|
cc9fb1497d
|
ecp5: Groundwork for DCU support
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-15 11:30:27 +00:00 |
|
Eddie Hung
|
2d39cde17b
|
Merge remote-tracking branch 'origin/master' into timingapi
|
2018-11-13 12:12:11 -08:00 |
|
Eddie Hung
|
3b2b15dc4a
|
Merge pull request #107 from YosysHQ/router_improve
Major rewrite of "router1"
|
2018-11-13 11:39:51 -08:00 |
|
David Shah
|
959d163ba7
|
ecp5: Improve delay estimates
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-13 14:27:23 +00:00 |
|
Pedro Vanzella
|
710ea1b265
|
Mark getArchOptions as override in derived classes
|
2018-11-13 11:03:48 -02:00 |
|
Clifford Wolf
|
06e0e1ffee
|
Various router1 fixes, Add BelId/WireId/PipId::operator<()
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-11-13 05:05:56 +01:00 |
|
David Shah
|
d3ad522bfe
|
ecp5: Copy clock constraints during global promotion
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-12 14:03:58 +00:00 |
|
David Shah
|
fc5e6bec9a
|
timing: Add support for clock constraints
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-12 14:03:58 +00:00 |
|
David Shah
|
11579a1046
|
ecp5: EBR clocking fix
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-12 14:03:58 +00:00 |
|
David Shah
|
8af86ff37d
|
ecp5: Update arch to new timing API
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-12 14:03:58 +00:00 |
|
Clifford Wolf
|
6002a0a80a
|
clangformat
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-11-11 19:48:15 +01:00 |
|
Clifford Wolf
|
f93129634b
|
Add getConflictingWireWire() arch API, streamline getConflictingXY semantic
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-11-11 17:28:41 +01:00 |
|
David Shah
|
9e5aded5c6
|
ecp5: Fix 85k PLL_LR
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-11 15:12:27 +00:00 |
|
Clifford Wolf
|
d2bdb670c0
|
Add getConflictingPipWire() arch API, router1 improvements
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2018-11-11 11:34:38 +01:00 |
|
Miodrag Milanovic
|
0ad5197ff4
|
show 4th tresllis_io in tile bounds
|
2018-11-11 08:25:54 +01:00 |
|
David Shah
|
04f9b87101
|
ecp5: Allow setting IO SLEWRATE
Signed-off-by: David Shah <dave@ds0.me>
|
2018-11-01 20:41:51 +00:00 |
|
David Shah
|
e005cc6754
|
ecp5: Add PLL support
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-31 19:52:41 +00:00 |
|
David Shah
|
24a2feda30
|
ecp5: Separate global promotion and routing
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-31 16:22:34 +00:00 |
|
David Shah
|
c782f07b1b
|
ecp5: Add IO buffer insertion
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-31 11:30:09 +00:00 |
|
David Shah
|
db0646be8a
|
ecp5: Adding LPF parser
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-31 10:48:54 +00:00 |
|
David Shah
|
0ac48c6a08
|
ecp5: DSP fixes
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-22 16:18:29 +01:00 |
|
David Shah
|
535a6f625a
|
ecp5: Working on DSPs
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-22 11:19:59 +01:00 |
|
David Shah
|
1a06f4b2bd
|
ecp5: Adding DSP support
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-21 20:07:18 +01:00 |
|
David Shah
|
b5faa7ad10
|
ecp5: Implement ECP5 equivalent of c9059fc
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-21 17:15:34 +01:00 |
|
David Shah
|
1cde208090
|
clangformat
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-16 14:37:58 +01:00 |
|
David Shah
|
8aac6db44b
|
ecp5: Add support for correct tile naming in all variants
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-16 14:37:24 +01:00 |
|
David Shah
|
3aa3f5d796
|
ecp5: Add DP16KD timing analysis
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-16 13:30:23 +01:00 |
|
David Shah
|
1fc2318c53
|
ecp5: Optimise DCC placement
Signed-off-by: David Shah <davey1576@gmail.com>
|
2018-10-14 13:22:47 +01:00 |
|
David Shah
|
bda94aa5a5
|
ecp5: Fix BRAM tile names
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-11 11:51:17 +01:00 |
|
David Shah
|
848ce6d41c
|
ecp5: Fixing BRAM initialisation
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-10 17:21:37 +01:00 |
|
David Shah
|
f7466110a5
|
ecp5: Working on BRAM initialisation
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-09 13:13:16 +01:00 |
|
David Shah
|
d716292e3d
|
ecp5: BRAM improvements with constant/inverted inputs
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-06 15:59:22 +01:00 |
|
David Shah
|
cd688a2784
|
ecp5: Fixing EBR constant tie-offs
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-05 16:47:03 +01:00 |
|
David Shah
|
85a95ec250
|
ecp5: Bitstream gen for DP16KD BRAM
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-05 15:53:41 +01:00 |
|
David Shah
|
56ab547aeb
|
ecp5: Infrastructure for BRAM bitstream gen
Signed-off-by: David Shah <dave@ds0.me>
|
2018-10-05 14:36:16 +01:00 |
|