* Himbaechel Gowin: Add support for CLKDIV and CLKDIV2
* Himbaechel Gowin: Add support for CLKDIV and CLKDIV2
* Gowin Himbaechel: HCLK Bug fixes and corrections
DQCE and DCS primitives are added.
DQCE allows the internal logic to enable or disable the clock network in
the quadrant. When clock network is disabled, all logic drivern by this
clock is no longer toggled, thus reducing the total power consumtion of
the device.
DCS allows you to select one of four sources for two clock wires (6 and 7).
Wires 6 and 7 have not been used up to this point.
Since "hardware" primitives operate strictly in their own quadrants,
user-specified primitives are converted into one or more "hardware"
primitives as needed.
Also:
- minor edits to make the most of helper functions like connectPorts()
- when creating bases, the corresponding constants are assigned to the
VCC and GND wires, but for now huge nodes are used because, for an
unknown reason, the constants mechanism makes large examples
inoperable. So for now we remain on the nodes.
Compatible with older Apicula databases.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
It was not taken into account that there are only 6 ALUs per cell. As a
result, on complex designs where ALUs and LUT-based memory are involved
and there are many LUTs (like in the RISCV emulator), there were
sometimes false positives about placement conflicts.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The statement in the Gowin documentation that in the reading mode
"READ_MODE=0" the output register is not used and the OCE signal is
ignored is not confirmed by practice - if the OCE was left unconnected
or connected to the constant network, then a change in output data was
observed even with CE=0, as well as the absence of such at CE=1.
Synchronizing CE and OCE helps and the memory works properly in complex
systems such as RISC-V emulation and i8080 emulation (with 32K RAM and
16K BSRAM based ROM), but there is no theoretical basis for this fix, so
it is a hack.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
For pROM(X9) primitives in images generated by Gowin IDE, there is an
interesting recommunication of inputs depending on the data bit depth.
For example, in some cases, a high logical level may be applied to the
Write Enable input, which, let’s say, is not entirely usual for Read
Only memory.
Here we will do similar manipulations.
In addition, several minor bug fixes are included:
- Fixed bit numbering for non-X9 series primitives.
- Fixed decoder generation for BLKSEL - do not assume unused inputs are
connected to GND.
- Use default values for BSRAM parameters - don't assume their
mandatory presence.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
As the board on the GW1N-1 chip becomes a rarity, its replacement is the
Tangnano1k board with the GW1NZ-1 chip. This chip has a unique mechanism
for turning off power to important things such as OSC, PLL, etc.
Here we introduce a primitive that allows energy saving to be controlled
dynamically.
We also bring the names of some functions to uniformity.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
In the images generated by Gowin IDE, the signals for dynamic BSRAM
block selection (BLKSEL[2:0]) are not always connected directly to the
ports - some chips add LUT2, LUT3 or LUT4 to turn these signals into
Clock Enable. Apparently there are chips with an error in the operation
of these ports.
Here we make such a decoder instead of using ports directly.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
It seems that the internal registers on the BSRAM output pins in
READ_MODE=1'b1 (pipeline) mode do not function properly because in the
images generated by Gowin IDE an external register is added to each pin,
and the BSRAM itself switches to READ_MODE=1'b0 (bypass) mode .
This is observed on Tangnano9k and Tangnano20k boards.
Here we repeat this fix.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Add description of BSRAM harness
In some cases, Gowin IDE adds a number of LUTs and DFFs to the BSRAM. Here we are trying to add similar elements.
More details with pictures: https://github.com/YosysHQ/apicula/blob/master/doc/bsram-fix.md
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
When multiplying 36 bits by 36 bits using four 18x18 multipliers, the
sign bits of the higher 18-bit parts of the multipliers were correctly
switched, but what was incorrect was leaving the sign bits of the lower
parts of the multipliers uninitialized. They now connect to VSS.
Addresses https://github.com/YosysHQ/apicula/issues/242
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Do not search for pads if the signal source for the PLL is something
other than the IO pin - these are guaranteed to already be placed and
have a bound Bel.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
If the CLKIN input of the PLL is connected to a special pin, then it
makes sense to try to place the PLL so that it uses a direct implicit
non-switched connection to this pin.
The transfer of information about pins for various purposes has been
implemented (clock input signal, feedback, etc), but so far only CLKIN
is used.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
For the following primitives:
- PADD9
- PADD18
- MULT9X9
- MULT18X18
- MULT36X36
- MULTALU18X18
- MULTALU36X18
- MULTADDALU18X18
- ALU54D
packing and processing of fixed wires between macro and between DSP
blocks is implemented.
Clusters of DSP and macro blocks are processed using custom placement of
cluster elements.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Corrects the situation when it is impossible to use IOBUF with two
IOLOGIC elements at the same time - input and output.
Addresses https://github.com/YosysHQ/nextpnr/issues/1275
This is done by dividing one IOLOGIC Bel into two - input IOLOGIC and
output IOLOGIC plus checking for compatibility of the cells located
there.
At the moment, this check is simple and allows only the combination of
DDR and DDRC primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
A small improvement - do not waste time analyzing already processed
networks in the previous step (and possibly steps).
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Semi-dual port BSRAM (in Gowin terminology) has the same feature as
Single Port - the CE and OCE signals must be synchronized.
Such a sin has not yet been noticed for Dual Port.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
