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268 Commits

Author SHA1 Message Date
gatecat
ecf24201ec interchange: Add wire types to chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-30 11:07:14 +01:00
gatecat
3fd1ee7757
Merge pull request #683 from antmicro/interchange-allow-loc-keyword 
interchange: allow LOC keyword in XDC files
 2021-04-20 14:12:14 +01:00
Jan Kowalewski
d1548ed317 interchange: allow LOC keyword in XDC files 
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
 2021-04-20 14:35:15 +02:00
gatecat
18459a9e4c interchange: Handle disconnected/missing cell pins 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-19 10:46:35 +01:00
gatecat
872b3aa63d interchange: Add default cell connections to chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-19 10:16:26 +01:00
gatecat
d4aac6586c Add Python bindings for placement tests 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-15 10:00:45 +01:00
gatecat
8f5185c381
Merge pull request #678 from acomodi/initial-fasm-generation 
interchange: add FASM generation target and clean-up tests
 2021-04-14 14:28:01 +01:00
Alessandro Comodi
dfc9c3df8c interchange: add FASM generation target and clean-up tests 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-04-14 14:36:07 +02:00
gatecat
4e346ecfba Hash table refactoring 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-14 10:30:19 +01:00
gatecat
06e54f08e6 interchange: Allow pseudo-cells with no input pins 
These are used for the LUT-as-GND-driver pseudo-pips in the Nexus arch,
which will probably be required for UltraScale too.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-13 10:58:41 +01:00
gatecat
fc15105643 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-12 10:26:39 +01:00
gatecat
93e34b8754 interchange: Disambiguate cell and bel pins when creating Vcc ties 
The pins created for tieing to Vcc were being named after the bel pin,
relying on the fact that Xilinx names cell and bel pins differently for
LUTs. This isn't true for Nexus devices which uses the same names for
both, and was causing a failure as a result.

This uses a "PHYS_" prefix that's highly unlikely to appear in a cell
pin name to disambiguate.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-09 10:26:32 +01:00
Keith Rothman
ae2f7551c1 [interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
3200026e1f [interchange] Remove requirement to have wire_lut. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
c2a6f6ce62 [interchange] Fix invalid use of local variables due to refactoring. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
8773c645ca [interchange] Prevent site router from generating incorrect LUTs. 
The previous logic tied LUT input pins to VCC if a wire was unplacable.
This missed a case where the net was present to the input of the LUT,
but a wire was still not legal.  This case is now prevented by tying the
output of the LUT to an unused net.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
c11ad31393 [interchange] Scale edge cost of pseudo pips. 
Previous pseudo pips were the same cost as regular pips, but this is
definitely too fast, and meant that the router was prefering them.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
9b82ded77b [interchange] Fix missing inline methods in site_arch.impl.h 
getBelPinWire and getBelPinType are marked as always inline, but were
not defined in a header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
90aa1d3b7e [interchange] Disallow site edges during general routing. 
This prevents the general router from routing through sites, which is
not legal in FPGA interchange.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman
0d41fff3a7 [interchange] Add crude pseudo pip model. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
gatecat
ff449ca997
Merge pull request #661 from litghost/document_site_router 
[interchange] Add some documentation for the site router.
 2021-04-06 09:20:03 +01:00
gatecat
8e0d8df791
Merge pull request #657 from acomodi/interchange-counter-multi-board 
interchange: counter: testing on multiple boards
 2021-04-06 08:12:02 +01:00
Keith Rothman
4301e4705b [interchange] Add some documentation for the site router. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-05 15:15:48 -07:00
Keith Rothman
009d3b64b6 [interchange] Update to v6 of FPGA interchange chipdb. 
Changes:
 - Adds LUT output pin to LutBelPOD.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-01 15:24:06 -07:00
Alessandro Comodi
366f8782cb interchange: counter: testing on multiple boards 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-04-01 10:23:07 +02:00
gatecat
ec98fee1ee
Merge pull request #646 from YosysHQ/gatecat/nexus-cmake 
fpga_interchange: Add CMake support for Nexus/prjoxide
 2021-03-31 15:14:51 +01:00
gatecat
3678eff5dc interchange: Fix nexus cmake review comments 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-31 10:11:09 +01:00
Keith Rothman
8675945b26 Fix bug where DedicateInterconnect incorrectly allows some placement. 
This occurs when the driver pin and sink pin are part of the same site,
but not reachable with site routing only.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-30 13:24:39 -07:00
Keith Rothman
7e47af1085 [interchange] Fix site pip check for drivers. 
Previous code allowed router to entire sites with no sinks.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-30 10:04:18 -07:00
gatecat
a003aae7c2 interchange: Split xc7 and nexus chipdb cmake 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 16:31:51 +01:00
gatecat
ecfaae7f9e interchange: Add Nexus LUT test 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 16:31:51 +01:00
gatecat
b6b8959397 interchange: Add Nexus to CI 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 16:31:51 +01:00
gatecat
3cb5e81d50 interchange: Add CMake support for Nexus/prjoxide 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 16:31:51 +01:00
gatecat
8863b962fd interchange: Fix illegal placements 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 15:28:19 +01:00
gatecat
692d7dc26d
Merge pull request #645 from litghost/add_counter_and_ram 
FPGA interchange: Add counter and ram tests
 2021-03-29 18:23:16 +01:00
Alessandro Comodi
b5ba3ee9ee interchange: add archcheck tests to all-device-test target 
This increases parallelism and should make the FPGA interchange CI
faster

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-26 15:11:03 +01:00
Keith Rothman
f33d02dca9 Update README with latest develpment progress. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:56:15 -07:00
Keith Rothman
55c9d43c70 interchange: Fix bug in site router where a bad solution isn't remove. 
This resulted in valid site routing solutions being missed.  Underlying
bug was an off-by-one error when unwinding a failed solution.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:56:14 -07:00
Keith Rothman
c8dccd3e7b Implement debugging tools for site router. 
- Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire
 - Adds "explain_bel_status", which should be an exhaustive diagnostic
   of the status of a BEL placement.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:56:11 -07:00
Keith Rothman
cc4f2b4516 Add some FIXME's around VCC assumption in LUT logic. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:13 -07:00
Keith Rothman
bbe1881293 Add targets to generate YAML outputs for DeviceResource files. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:13 -07:00
Keith Rothman
91ca5f110b Re-work LUT mapping logic to only put VCC pins when required. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:13 -07:00
Keith Rothman
5dda3a14ff Fixup some of the re-mapping logic. 
- Add IDEMPOTENT_CHECK define to perform some expected idempotent
   operations more than once to verify they work as expected.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:13 -07:00
Keith Rothman
77bc2f9130 Add initial handling of local site inverters and constant signals. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:09 -07:00
Keith Rothman
5e96740451 [FPGA interchange] Small fix to get_net_type. 
If get_net_type was called before the driver was placed, it could return
the wrong value.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:14:53 -07:00
Keith Rothman
22fb2c1548 Enable counter tests and add RAM tests. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:14:53 -07:00
Alessandro Comodi
9f28fa4e75 gh-actions: interchange: multiple jobs, one for each device 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-24 15:37:03 +01:00
Alessandro Comodi
1a774a0526 interchange: examples: remove unused makefiles 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-24 15:37:02 +01:00
Alessandro Comodi
b6d2a59fc2 interchange: devices: bel_bucket_seeds -> device_config 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-23 21:06:01 +01:00
Alessandro Comodi
15e945aa1c interchange: added boards and group testing across multiple boards 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-23 21:05:58 +01:00
Alessandro Comodi
4812092cdb fpga_interchange: add test data for new architectures 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-23 20:36:23 +01:00
Alessandro Comodi
658dadaa70 fpga_interchange: use higher java heap space 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-23 20:36:23 +01:00
Alessandro Comodi
336d31cbcf fpga_interchange: add more devices 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-23 20:36:23 +01:00
gatecat
3cc50a5744
Merge pull request #644 from litghost/add_global_buffers 
[FPGA interchange] Add support for global buffers from chipdb.
 2021-03-23 17:33:55 +00:00
gatecat
323da87dec
Merge pull request #643 from litghost/id_constants 
[FPGA interchange] Convert some string constants to IdString.
 2021-03-23 17:33:40 +00:00
gatecat
2300d81c3c
Merge pull request #640 from litghost/inversion_logic 
Initial inverter logic for FPGA interchange
 2021-03-23 16:59:35 +00:00
gatecat
8c85e648df
Merge pull request #639 from litghost/parameter_iteration 
Update parameter processing based on new DeviceResources metadata
 2021-03-23 16:51:28 +00:00
Keith Rothman
720f64ea60 [FPGA interchange] Add support for global buffers from chipdb. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:41:45 -07:00
Keith Rothman
0dd93035e4 [FPGA interchange] Convert some string constants to IdString. 
Also add some optional diagnostic prints for cell -> BEL pin mapping.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:38:37 -07:00
gatecat
b7bf2c706f
Merge pull request #642 from YosysHQ/gatecat/missing-cell-pin 
interchange: Add nice error for missing cell pins
 2021-03-23 16:34:10 +00:00
Keith Rothman
831b94cdac Initial version of inverter logic. 
For now just implements some inspection capabilities, and the site
router (for now) avoids inverted paths.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:03:07 -07:00
Keith Rothman
ae71206e1f Update FPGA interchange chipdb to v4 with inverter data. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:01:45 -07:00
Keith Rothman
8a50b02b9b Use new parameter definition data in FPGA interchange processing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:01:43 -07:00
Keith Rothman
af1fba9f52 Update latest version of FPGA interchange schema. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:00:58 -07:00
gatecat
79400756f5 interchange: Add nice error for missing cell pins 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-23 15:40:34 +00:00
Keith Rothman
8d1eb0a195 Initial lookahead for FPGA interchange. 
Currently the lookahead is disabled by default because of the time to
compute and RAM usage.  However it does appear to work reasonably well
in testing.  Further effort is required to lower RAM usage after initial
computation, and explore trade-off for cheaper time to compute.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 08:16:50 -07:00
gatecat
9ef412c2cc
Merge pull request #638 from litghost/fixup_physical_netlist_writer 
Correct some bugs in writing of physical netlist w.r.t. site sources.
 2021-03-22 18:32:26 +00:00
gatecat
a3ed97c0db
Merge pull request #637 from litghost/refine_site_router 
Refine site router
 2021-03-22 18:32:04 +00:00
gatecat
e8d36bf5bd
Merge pull request #634 from litghost/add_get_bel_pin_type 
Add getBelPinType to Python interface.
 2021-03-22 18:31:48 +00:00
Keith Rothman
32f2ec86c4 Rework FPGA interchange site router. 
The new site router should be robust to most situations, and isn't
significantly slower with the use of caching.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-22 09:54:49 -07:00
Keith Rothman
0f4014615c Add missing dependencies to CMake targets. 
- Add additional targets useful for various situations.
 - Have counter test use common remap.v file.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-22 09:47:33 -07:00
Keith Rothman
06bcde6243 Correct some bugs in writing of physical netlist w.r.t. site sources. 
Local site sources should have their driving BEL pin included in the net
so that the site wire is driven by an output BEL pin.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-22 09:46:43 -07:00
Keith Rothman
4cd74bba2c Add getBelPinType to Python interface. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-22 09:25:45 -07:00
Keith Rothman
e7d81913a4 Add "checkPipAvailForNet" to Arch API. 
This is important for distiguishing valid pseudo pips in the FPGA
interchange arch. This also avoids a double or triple lookup of
pip->net map.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-22 09:17:55 -07:00
Keith Rothman
db12a83ced Add pseudo pip data to chipdb (with schema bump). 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-22 09:33:12 +00:00
Keith Rothman
2cd5bacca0 Refactor header structures in FPGA interchange Arch. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-19 21:36:06 -07:00
Keith Rothman
f4dc67879e Fixup GUI link dependencies on headers from libraries. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-18 14:00:19 -07:00
Alessandro Comodi
01a95faf21 fpga_interchange: temporarily disable failing test 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-17 10:32:35 +01:00
Alessandro Comodi
f6583f7ecc fpga_interchange: minor fixes and comments addition 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 22:59:20 +01:00
Alessandro Comodi
c1e668f823 fpga_interchange: address review comments 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 22:02:06 +01:00
Alessandro Comodi
f9e9fadbc8 github-actions: use capnp v0.8.0 
This also updates the note in the README for the FPGA interchange

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 16:57:07 +01:00
Alessandro Comodi
f63a9a48a4 fpga_interchange: re-add README with updated instructions 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 15:39:02 +01:00
Alessandro Comodi
f52b5b39ed fpga_interchange: tests: add techmap optional source file 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 15:39:02 +01:00
Alessandro Comodi
3f3cabea2d fpga_interchange: add bbasm step and archcheck 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 15:39:02 +01:00
Alessandro Comodi
0b62e540a3 fpga_interchange: address review comments 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 15:39:02 +01:00
Alessandro Comodi
bd2da27e4e fpga_interchange: tests: added comment and fixed XDC 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 15:39:02 +01:00
Alessandro Comodi
e5cc03965e fpga_interchange: chipdb: use generic patching function 
Also moved the RapidWright invocation script path under a CMake variable

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 15:39:02 +01:00
Alessandro Comodi
490fdb0a1c fpga_interchange: cmake: generate only one device family 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 15:39:01 +01:00
Alessandro Comodi
77ffdd7fd4 fpga_interchange: tests: add cmake functions 
Also move all tests in a tests directory

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 15:39:01 +01:00
Alessandro Comodi
d77d0ff34a fpga_intrchange: add cmake infrastructure to generate chipdbs 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 15:39:01 +01:00
Keith Rothman
351ca3b5ea Use NEXTPNR_NAMESPACE macro's now that headers are seperated. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-15 18:49:12 +00:00
Keith Rothman
fe4608386e Split nextpnr.h to allow for linear inclusion. 
"nextpnr.h" is no longer the god header.  Important improvements:

 - Functions in log.h can be used without including
   BaseCtx/Arch/Context. This means that log_X functions can be called
   without included "nextpnr.h"

 - NPNR_ASSERT can be used without including "nextpnr.h" by including
   "nextpnr_assertions.h".  This allows NPNR_ASSERT to be used safely in
   any header file.

 - Types defined in "archdefs.h" are now available without including
   BaseCtx/Arch/Context.  This means that utility classes that will be
   used inside of BaseCtx/Arch/Context can be defined safely in a
   self-contained header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-15 09:05:23 -07:00
gatecat
fba71bd182 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-03 10:39:47 +00:00
Keith Rothman
71b92cb813 Update FPGA interchange README. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 11:01:22 -08:00
Keith Rothman
78748a67be For now just return false in the site router. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 11:01:22 -08:00
Keith Rothman
cfa449c3f3 Initial LUT rotation logic. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 11:01:22 -08:00
Keith Rothman
9cbfd0b967 Add counter test. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 11:01:22 -08:00
gatecat
23413a4d12 Fix compiler warnings introduced by -Wextra 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-25 15:15:25 +00:00
Keith Rothman
a30043c8da Fix assorted bugs in FPGA interchange. 
Fixes:
 - Only use map constant pins during routing, and not during placement.
 - Unmapped cell ports have no BEL pins.
 - Fix SiteRouter congestion not taking into account initial expansion.
 - Fix psuedo-site pip output.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:28 -08:00
Keith Rothman
184665652e Finish dedicated interconnect implementation. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:28 -08:00
Keith Rothman
5574455d2a Working FF example now that constant merging is done. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:28 -08:00
Keith Rothman
2fc353d559 Add initial logic for handling dedicated interconnect situations. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:28 -08:00
Keith Rothman
cd8297f54d Move RapidWright git URI back to upstream. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:28 -08:00
Keith Rothman
5c6e231412 Remove some signedness warnings. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:28 -08:00
Keith Rothman
46b38f8a40 Fix reference copy. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:27 -08:00
Keith Rothman
3ccb164f2a Run "make clangformat". 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:27 -08:00
Keith Rothman
15459cae91 Initial working constant network support! 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:27 -08:00
Keith Rothman
cf554f9338 Add constant network test case. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:27 -08:00
Keith Rothman
3e5a23ed5b Add tests to confirm constant routing import. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:27 -08:00
Keith Rothman
761d9d9229 Correct some bugs in the create_bba Makefile. 
Also add debug_test target to debug archcheck.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:27 -08:00
Keith Rothman
40df4f4f65 Add initial constant network support to FPGA interchange arch. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:27 -08:00
Keith Rothman
423a10bc31 Change CellInfo in getBelPinsForCellPin to be const. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:08:54 -08:00
gatecat
7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad 
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 11:31:33 +00:00
Keith Rothman
c21e23b3eb Fix sign mismatch. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-18 14:08:22 -08:00
Keith Rothman
e138a6c56d Do some spell checking on site_router.cc 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-18 13:34:06 -08:00
Keith Rothman
4766e889c0 Add some utility methods for site instance access. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-18 13:26:52 -08:00
Keith Rothman
532954847a Update README's with latest instructions and features. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-18 13:01:42 -08:00
Keith Rothman
8ef5411f70 Add utility targets for getting plain text outputs. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:17 -08:00
Keith Rothman
b3dcc9d507 Add IOSTANDARD to ports. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:17 -08:00
Keith Rothman
5833c90210 Emit fixed attributes to output physical netlist. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:17 -08:00
Keith Rothman
558a753d3d Refactor "get only from iterator" to a utility. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:17 -08:00
Keith Rothman
9e0ca72827 Keep all build artifacts under create_bba/build. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
Keith Rothman
f9bd692f75 Change how package pin IO sites are selected. 
The first site type that matches is now selected, under the premise that
the early site types are more general.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
Keith Rothman
cc687b3b72 Change makefiles to build a FPGA interchange BBA. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
Keith Rothman
5a7f83c705 Add examples invoking FPGA interchange nextpnr. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
Keith Rothman
7c1544f4d8 Continue fixes. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
Keith Rothman
6f1c835221 Disable traversal limit when reading logical netlist. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
Keith Rothman
c385321248 Add initial site router. 
This site router likely cannot handle the full problem space.  It may
need to be replaced with a more generalize approach as testing
continues.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
Keith Rothman
a7421399f7 Working on standing up initial constraints system. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
gatecat
399c24c805 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-17 10:45:23 +00:00
gatecat
da1ecf0813
Merge pull request #586 from litghost/add_cell_bel_mapping_only 
Add Cell -> BEL Pin maps to FPGA interchange arch.
 2021-02-17 10:16:45 +00:00
Keith Rothman
26a187e5eb Require --package when arch BBA contains multiple packages. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-16 14:00:01 -08:00
Keith Rothman
bb4fa7af5b [FPGA Interchange] Add Cell -> BEL Pin maps. 
This also expands the FPGA interchange Arch BBA to include placement
constraints, but doesn't implement them yet.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-16 09:37:19 -08:00
gatecat
c7c13cd95f Remove isValidBelForCell 
This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.

In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).

Longer term, removing this API makes things a bit cleaner for a new
validity checking API.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-16 13:31:36 +00:00
Keith Rothman
2c7ee44046 Move CMake logic into fpga-interchange-schema. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-15 09:54:58 -08:00
Keith Rothman
6b04fd1524 Small fixes from review. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-15 09:54:58 -08:00
Keith Rothman
664407089b Add FPGA interchange frontend and backend. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-15 09:54:58 -08:00
gatecat
1b6cdce925
Merge pull request #575 from YosysHQ/gatecat/belpin-2 
Support for cell pin to bel pin mappings
 2021-02-15 09:38:22 +00:00
Keith Rothman
82ab3c1aad Run "make clangformat". 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-12 10:31:05 -08:00
Keith Rothman
8a860857ea Remove capnp and libz for XDC parser PR. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-12 10:31:05 -08:00
Keith Rothman
c96d0f225c Refactor XDC parser into a little class for testing purposes. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-12 10:31:04 -08:00
Keith Rothman
d987bd2997 Add unknown handles to convert [0] to "[0]". 
Tcl reads something like "set port [get_ports x[0]]" as "invoke proc 0
with zero arguments", rather than just "[0]".  To prevent exposing
non-Tcl users this, "[<number>]" just return themselves.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-12 10:31:04 -08:00
Keith Rothman
a0bd313139 Add FPGA interchange XDC parser. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-12 10:31:04 -08:00
Keith Rothman
99e397000c Add getBelHidden and add some missing "override" statements. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-11 14:58:02 -08:00
gatecat
85bb108ba4 Add getBelPinsForCellPin to Arch API 
This is a basic implementation, without considering "M of N"
arrangements (e.g. for LUT permuation where you only want to route to 1
out of 4/6 sinks) or using a type other than IdString to identify bel
pins.

But this is also enough to start working out where in nextpnr will break
due to removing the 1:1 cell:bel pin cardinality, as a next step.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-10 11:54:54 +00:00
D. Shah
9deb9e6e85 interchange: Base on ArchAPI 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-08 10:41:03 +00:00
Keith Rothman
a0ee42833b Add RelSlice::ssize and use it when comparing with signed ints. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-05 10:12:13 -08:00
Keith Rothman
9557047e5e Move all string data into BBA file. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-05 09:22:55 -08:00
Keith Rothman
ca32e935a6 Use RelSlice instead of RelPtr in cases where sizes are present. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:34 -08:00
Keith Rothman
f1ee2fde58 Update APIs to conform to style guide. 
- Change non-Arch methods to snake_case
 - Adds some utility functions to for accessing bel_data.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:34 -08:00