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Author SHA1 Message Date
SpaceCat-Chan
f7fc239f75 improve partition sanity check quality of life 2023-12-06 17:45:20 +00:00
SpaceCat-Chan
3694632aa4 use new arc type in partitioner 2023-12-06 17:45:20 +00:00
SpaceCat-Chan
908d7ef69a only search pips inside partition bounds 2023-12-06 17:45:20 +00:00
Lofty
6213b13277 awooter: wip 2023-12-06 17:45:20 +00:00
SpaceCat-Chan
b333080715 finalize downhill iterator 2023-12-06 17:45:20 +00:00
SpaceCat-Chan
2ff491c717 create downhill iter wrapper 2023-12-06 17:45:20 +00:00
Lofty
bc7f7845d2 awooter: further clean up 2023-12-06 17:45:20 +00:00
Lofty
a16247d512 awooter: add Arc struct 2023-12-06 17:45:20 +00:00
SpaceCat-Chan
319d1c4620 split partitioning code into seperate file 2023-12-06 17:45:20 +00:00
SpaceCat-Chan
9b4c6966be split arc extraction into function 2023-12-06 17:45:20 +00:00
Lofty
2c1a9d18ed awooter: clean up unused code 2023-12-06 17:45:20 +00:00
Lofty
cb7dba6dd5 awooter: return of the progress bar 2023-12-06 17:45:20 +00:00
SpaceCat-Chan
ae756e2d8c fix bug in split_line_over_x 2023-12-06 17:45:20 +00:00
Lofty
1cc00308dc awooter: simple time measurement 2023-12-06 17:45:20 +00:00
SpaceCat-Chan
2d3c05da85 make partitioner run in parallel over nets 2023-12-06 17:45:20 +00:00
Lofty
ba9067afaf awooter: atomics instead 2023-12-06 17:45:20 +00:00
Lofty
268906819d awooter: better locking 2023-12-06 17:45:20 +00:00
Lofty
1077cd3654 awooter: properly parallelise 2023-12-06 17:45:20 +00:00
Lofty
c00fba75e9 awooter: clamp pip indices 2023-12-06 17:45:20 +00:00
Lofty
2a18fe58c6 awooter: cargo fmt 2023-12-06 17:45:20 +00:00
Lofty
f1a4848c0f awooter: parallelise partitioning 2023-12-06 17:45:20 +00:00
Lofty
873a70ddd0 awooter: refactor and bugfix 
Co-authored-by: Spacecat-Chan <49094338+SpaceCat-Chan@users.noreply.github.com>
 2023-12-06 17:45:20 +00:00
Lofty
c8a2b842d6 awooter: further prettify 2023-12-06 17:45:20 +00:00
Lofty
e64cd668b2 awooter: prettify 2023-12-06 17:45:20 +00:00
Lofty
d50ab6139c awooter: net-based partitioner 2023-12-06 17:45:20 +00:00
Lofty
f64caaae24 awooter: wire storage and some cleanup 2023-12-06 17:45:20 +00:00
Lofty
4a0406420b awooter: 'better' FFI API 2023-12-06 17:45:20 +00:00
Lofty
b92a1bf52d awooter: fix an API soundness issue 2023-12-06 17:45:20 +00:00
Lofty
0cc3245d4b awooter: partition experiment code 2023-12-06 17:45:20 +00:00
Lofty
60cc6b7765 awooter: add net import code 2023-12-06 17:45:20 +00:00
Jubilee
195d344d9a Specify PROFILE when importing awooter 
Otherwise CMake and Corrosion get confused about how to put things together.
 2023-12-06 17:45:20 +00:00
Lofty
d5d6a07c34 awooter: highly, highly WIP 2023-12-06 17:45:20 +00:00
gatecat
6d9322457e static: Reduce stddev of initial solution 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-26 16:51:47 +01:00
YRabbit
c13b34f20e gowin: Himbaechel. Add BSRAM for all chips. 
The following primitives are implemented for the GW1N-1, GW2A-18,
    GW2AR-18C, GW1NSR-4C, GW1NR-9C, GW1NR-9 and GW1N-4 chips:

    * pROM     - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
    * pROMX9   - read only memory - (bitwidth: 9, 18, 36).
    * SDPB     - semidual port    - (bitwidth: 1, 2, 4, 8, 16, 32).
    * SDPX9B   - semidual port    - (bitwidth: 9, 18, 36).
    * DPB      - dual port        - (bitwidth: 16).
    * DPX9B    - dual port        - (bitwidth: 18).
    * SP       - single port      - (bitwidth: 1, 2, 4, 8, 16, 32).
    * SPX9     - single port      - (bitwidth: 9, 18, 36).

    For GW1NSR-4C and GW1NR-9 chips, SP/SPX9 primitives with data widths
    of 32/36 bits are implemented using a pair of 16-bit wide
    primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-11-26 13:08:09 +01:00
YRabbit
90d4863dd4 gowin: Himbaechel. Add GW1NZ-1 BSRAM. 
The following primitives are implemented for the GW1NZ-1 chip:

* pROM     - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9   - read only memory - (bitwidth: 9, 18, 36).
* SDPB     - semidual port    - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B   - semidual port    - (bitwidth: 9, 18, 36).
* DPB      - dual port        - (bitwidth: 16).
* DPX9B    - dual port        - (bitwidth: 18).
* SP       - single port      - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9     - single port      - (bitwidth: 9, 18, 36).

Also:
 - The creation of databases for GW1NS-2 has been removed - this was not
   planned to be supported in Himbaechel from the very beginning and
   even examples were not created in apicula for this chip due to the
   lack of boards with it on sale.
 - It is temporarily prohibited to connect DFFs and LUTs into clusters
   because for some reason this prevents the creation of images on lower
   chips (placer cannot find the placement), although without these
   clusters the images are quite working. Requires further research.
 - Added creation of ALU with mode 0 - addition. Such an element is not
   generated by Yosys, but it is a favorite vendor element and its
   support here greatly simplifies the compilation of vendor netlists.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-11-26 13:08:09 +01:00
YRabbit
f2c280feda gowin: Himbaechel. Initial BSRAM support 
Only pROM/pROMX9 for now

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-11-26 13:08:09 +01:00
Miodrag Milanovic
e3f4578b3b CRLF -> LF eol 2023-11-23 09:22:07 +01:00
Miodrag Milanovic
ec60542ffd create wiremap for himbaechel arch 2023-11-23 09:22:07 +01:00
Miodrag Milanovic
1ec8e411d7 set render bound box, so grid is displayed 2023-11-23 08:21:26 +01:00
Miodrag Milanovic
0b8a93eed5 fix compile warning 2023-11-23 08:21:26 +01:00
gatecat
de3d5be8f0 python: Remove deprecated use of Py_SetProgramName 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-23 06:49:15 +01:00
Balint Cristian
7814f44883 Fix abstract class implementation for fpga_interchange 
Signed-off-by: Balint Cristian <cristian.balint@gmail.com>
 2023-11-23 06:49:01 +01:00
gatecat
6683fd4ada himbaechel: Fix when more then 32k unique node shapes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-22 17:11:27 +01:00
gatecat
55635cf2cd Update README 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-17 09:14:19 +01:00
gatecat
e2a887ef0d himbaechel: Switch default back to router1 for now 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-17 09:09:59 +01:00
gatecat
5bfe0dd1b1 himbaechel: Adding a xilinx uarch for xc7 with prjxray 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-14 17:12:09 +01:00
laanwj
a32ad13a86 ecp5: Don't segfault while packing FFs when DI port of TRELLIS_FF unconnected 
Currently a segfault happens when the DI port is not specified. Leaving
it unconnected is probably incorrect, but it shouldn't crash the placer.
Fix by adding a check.
 2023-11-14 11:55:51 +01:00
uis
a4d2244300 Fix printf formats 2023-11-13 13:59:51 +01:00
YRabbit
0106c3d299 gowin: Himbaechel. Diff io BUGFIX. 
Fixed incorrect use of attributes instead of parameters.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-11-13 13:59:28 +01:00
Lofty
506d5f9422 machxo2: less pessimistic delay prediction 2023-11-09 06:48:50 +01:00