Rowan Goemans
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098dcaedec
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timing: remove the articial clock delay inflation
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2024-09-24 08:57:21 +02:00 |
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Rowan Goemans
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0fce4b8f4e
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timing: lower clock_delay_fact to 1 to check if CI passes
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2024-09-24 08:57:21 +02:00 |
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Rowan Goemans
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25d64b2105
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timing_log: Fix logging indendation to match master
timing: Disable clock_skew analysis by default
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2024-09-24 08:57:21 +02:00 |
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Rowan Goemans
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bca6f6394a
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timing: Fix slack calculations
timing: Fix max_delay_by_domain_pair function
timing: Fix hold time check
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2024-09-24 08:57:21 +02:00 |
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Rowan Goemans
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86106cb49a
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timing: integrate c2c delays and cleanup code
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2024-09-24 08:57:21 +02:00 |
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Rowan Goemans
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fc3b2de8da
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timing: Add clock skew to arrival and required time
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2024-09-24 08:57:21 +02:00 |
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Rowan Goemans
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82ea65d984
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timing: Report min delay violated in timing logger
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2024-09-24 08:57:21 +02:00 |
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Rowan Goemans
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c25da06d03
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timing: Start identification of min_delay violations
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2024-09-24 08:57:21 +02:00 |
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Rowan Goemans
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44665a9c4d
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timing: Allow critical path traversal for shortest paths
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2024-09-24 08:57:21 +02:00 |
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Rowan Goemans
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8d0f52fbf9
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timing: Move towards DelayPairs for timing reporting (#1359)
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2024-09-11 07:23:46 +01:00 |
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rowanG077
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38d2a4b844
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tmg: Fix argument order in run method
Router 2 expects "update_route_delays" to be the first argument to `tmg.run`.
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2023-09-25 13:20:40 +02:00 |
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rowanG077
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240f89081f
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Add back error/warning for combinational loops
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2023-08-18 09:15:37 +02:00 |
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rowanG077
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d2a489d5e9
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Remove old timing analyser
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2023-08-18 09:15:37 +02:00 |
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rowanG077
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596873c302
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tmg: Add net_timings, crit path and slack hist
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2023-08-18 09:15:37 +02:00 |
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rowanG077
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8b51674a6b
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Add critical path report to modern timing engine
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2023-08-18 09:15:37 +02:00 |
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rowanG077
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914999673c
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Rip out budgets
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2023-06-20 10:57:10 +02:00 |
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Rowan Goemans
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5b958c4d80
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Analyse async paths in TimingAnalyser (#1171)
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2023-06-09 08:01:47 +02:00 |
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Maciej Kurc
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9000c41c4b
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Added the --ignore-rel-clk option to control timing checks for cross-domain paths, formatted code
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2022-09-20 14:40:40 +02:00 |
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Maciej Kurc
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9a61ad9234
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Augmented TimingAnalyser class with detection of clock to clock relations
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2022-08-30 17:30:58 +02:00 |
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gatecat
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49f178ed94
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Split up common into kernel,place,route
Signed-off-by: gatecat <gatecat@ds0.me>
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2022-04-08 13:42:54 +01:00 |
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