During general routing, the only site pips that can be allowed are those
which connect a site wire to the routing interface.
This might be too restrictive when dealing with architectures that
require more than one site PIPs to route from a driver within a site to the routing
interface (which is something that should be allowed in the
interchange).
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
These are used for the LUT-as-GND-driver pseudo-pips in the Nexus arch,
which will probably be required for UltraScale too.
Signed-off-by: gatecat <gatecat@ds0.me>
The pins created for tieing to Vcc were being named after the bel pin,
relying on the fact that Xilinx names cell and bel pins differently for
LUTs. This isn't true for Nexus devices which uses the same names for
both, and was causing a failure as a result.
This uses a "PHYS_" prefix that's highly unlikely to appear in a cell
pin name to disambiguate.
Signed-off-by: gatecat <gatecat@ds0.me>
The previous logic tied LUT input pins to VCC if a wire was unplacable.
This missed a case where the net was present to the input of the LUT,
but a wire was still not legal. This case is now prevented by tying the
output of the LUT to an unused net.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Previous pseudo pips were the same cost as regular pips, but this is
definitely too fast, and meant that the router was prefering them.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
getBelPinWire and getBelPinType are marked as always inline, but were
not defined in a header.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This prevents the general router from routing through sites, which is
not legal in FPGA interchange.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This occurs when the driver pin and sink pin are part of the same site,
but not reachable with site routing only.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This resulted in valid site routing solutions being missed. Underlying
bug was an off-by-one error when unwinding a failed solution.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
- Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire
- Adds "explain_bel_status", which should be an exhaustive diagnostic
of the status of a BEL placement.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
