gatecat
|
6455b5dd26
|
viaduct: Add support for GUIs
Signed-off-by: gatecat <gatecat@ds0.me>
|
2023-04-11 19:11:54 +02:00 |
|
Miodrag Milanovic
|
35eeaa7cc5
|
Add ramaining PIO tiles
|
2023-03-20 09:53:35 +01:00 |
|
Miodrag Milanovic
|
0ce72e1a31
|
Use TRELLIS primitives
|
2023-03-20 09:53:35 +01:00 |
|
Miodrag Milanovic
|
ad5f6fccaa
|
Use RelSlice, make more in line with ecp5 arch
|
2023-03-20 09:53:35 +01:00 |
|
gatecat
|
4111cc25d6
|
clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
|
2023-03-17 09:31:38 +01:00 |
|
Miodrag Milanovic
|
7ad9914e51
|
Extend chipdb with metadata
|
2023-03-16 13:37:23 +01:00 |
|
gatecat
|
76683a1e3c
|
refactor: Use constids instead of id("..")
Signed-off-by: gatecat <gatecat@ds0.me>
|
2022-02-16 17:09:54 +00:00 |
|
William D. Jones
|
064b6d808e
|
clangformat.
|
2021-12-16 17:09:29 -05:00 |
|
William D. Jones
|
d2ac6dffbc
|
machxo2: Correct which PIO wires get adjusted when writing text bitstream. Add verbose logging for adjustments.
|
2021-12-16 16:59:37 -05:00 |
|
William D. Jones
|
45c33e9dcf
|
machxo2: Add a special case for pips whose config bits are in multiple
tiles.
|
2021-07-01 09:36:02 -04:00 |
|
William D. Jones
|
ec239c8c35
|
machxo2: Hardcode a rule for emitting U_/D_ or G_ prefixes in ASCII output.
|
2021-07-01 09:36:01 -04:00 |
|
gatecat
|
2ffb081442
|
Fixing old emails and names in copyrights
Signed-off-by: gatecat <gatecat@ds0.me>
|
2021-06-12 13:22:38 +01:00 |
|
gatecat
|
579b98c596
|
Use hashlib for core netlist structures
Signed-off-by: gatecat <gatecat@ds0.me>
|
2021-06-02 14:27:56 +01:00 |
|
gatecat
|
23413a4d12
|
Fix compiler warnings introduced by -Wextra
Signed-off-by: gatecat <gatecat@ds0.me>
|
2021-02-25 15:15:25 +00:00 |
|
gatecat
|
8f5133d811
|
machxo2: Use snake_case for non-ArchAPI functions
Signed-off-by: gatecat <gatecat@ds0.me>
|
2021-02-12 10:36:59 +00:00 |
|
gatecat
|
3f7618283d
|
machxo2: Update with Arch API changes
Signed-off-by: gatecat <gatecat@ds0.me>
|
2021-02-12 10:36:59 +00:00 |
|
William D. Jones
|
f18df5ed59
|
machxo2: Don't write out config bits for cells without location info.
|
2021-02-12 10:36:59 +00:00 |
|
William D. Jones
|
da1b15d6f5
|
machxo2: Special-case left and right I/O wire names in ASCII generation.
|
2021-02-12 10:36:59 +00:00 |
|
William D. Jones
|
0250aaaddd
|
machxo2: clang format.
|
2021-02-12 10:36:59 +00:00 |
|
William D. Jones
|
0d00c10e2f
|
machxo2: Add bitstream generation for OSCH.
|
2021-02-12 10:36:59 +00:00 |
|
William D. Jones
|
884e7d9a98
|
machxo2: Add basic bitstream generation for PIC tiles and I/O.
|
2021-02-12 10:36:59 +00:00 |
|
William D. Jones
|
d485dc6ef6
|
machxo2: Add REGMODE to bitstream output.
|
2021-02-12 10:36:59 +00:00 |
|
William D. Jones
|
5415194b39
|
machxo2: Checkpoint commit for slice bitstream generation.
|
2021-02-12 10:36:59 +00:00 |
|
William D. Jones
|
cf2db7a4c4
|
machxo2: Write out pips to bitstream.
|
2021-02-12 10:36:59 +00:00 |
|
William D. Jones
|
56656b2b24
|
machxo2: Emit empty bitstream file.
|
2021-02-12 10:36:59 +00:00 |
|
William D. Jones
|
75f33e0c55
|
machxo2: Add stub bitstream writer plus support files.
|
2021-02-12 10:36:59 +00:00 |
|