X(L0_O)
X(L1_O)
X(L2_O)
X(L3_O)
X(L4_O)
X(L5_O)
X(L6_O)
X(L7_O)

X(L0_I0)
X(L0_I1)
X(L0_I2)
X(L0_I3)

X(L1_I0)
X(L1_I1)
X(L1_I2)
X(L1_I3)

X(L2_I0)
X(L2_I1)
X(L2_I2)
X(L2_I3)

X(L3_I0)
X(L3_I1)
X(L3_I2)
X(L3_I3)

X(L4_I0)
X(L4_I1)
X(L4_I2)
X(L4_I3)

X(L5_I0)
X(L5_I1)
X(L5_I2)
X(L5_I3)

X(L6_I0)
X(L6_I1)
X(L6_I2)
X(L6_I3)

X(L7_I0)
X(L7_I1)
X(L7_I2)
X(L7_I3)

X(L0_D)
X(L1_D)
X(L2_D)
X(L3_D)
X(L4_D)
X(L5_D)
X(L6_D)
X(L7_D)

X(L0_Q)
X(L1_Q)
X(L2_Q)
X(L3_Q)
X(L4_Q)
X(L5_Q)
X(L6_Q)
X(L7_Q)

X(RAM_WA0)
X(RAM_WA1)
X(RAM_WA2)
X(RAM_WA3)
X(RAM_WA4)
X(RAM_WA5)
X(RAM_WA6)
X(RAM_WA7)
X(RAM_WA8)

X(RAM_RA0)
X(RAM_RA1)
X(RAM_RA2)
X(RAM_RA3)
X(RAM_RA4)
X(RAM_RA5)
X(RAM_RA6)
X(RAM_RA7)
X(RAM_RA8)

X(RAM_WE0)
X(RAM_WE1)

X(RAM_DI0)
X(RAM_DI1)
X(RAM_DI2)
X(RAM_DI3)
X(RAM_DI4)
X(RAM_DI5)
X(RAM_DI6)
X(RAM_DI7)
X(RAM_DI8)
X(RAM_DI9)
X(RAM_DI10)
X(RAM_DI11)
X(RAM_DI12)
X(RAM_DI13)
X(RAM_DI14)
X(RAM_DI15)

X(RAM_DO0)
X(RAM_DO1)
X(RAM_DO2)
X(RAM_DO3)
X(RAM_DO4)
X(RAM_DO5)
X(RAM_DO6)
X(RAM_DO7)
X(RAM_DO8)
X(RAM_DO9)
X(RAM_DO10)
X(RAM_DO11)
X(RAM_DO12)
X(RAM_DO13)
X(RAM_DO14)
X(RAM_DO15)