/*
 *  nextpnr -- Next Generation Place and Route
 *
 *  Copyright (C) 2024  The Project Peppercorn Authors.
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#include <boost/algorithm/string.hpp>

#include "pack.h"

#define HIMBAECHEL_CONSTIDS "uarch/gatemate/constids.inc"
#include "himbaechel_constids.h"

NEXTPNR_NAMESPACE_BEGIN

void GateMatePacker::disconnect_if_gnd(CellInfo *cell, IdString input)
{
    NetInfo *net = cell->getPort(input);
    if (!net)
        return;
    if (net->name.in(ctx->id("$PACKER_GND"))) {
        cell->disconnectPort(input);
    }
}

void GateMatePacker::pack_io()
{
    // Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
    for (auto &port : ctx->ports) {
        if (!ctx->cells.count(port.first))
            log_error("Port '%s' doesn't seem to have a corresponding top level IO\n", ctx->nameOf(port.first));
        CellInfo *ci = ctx->cells.at(port.first).get();

        PortRef top_port;
        top_port.cell = nullptr;
        bool is_npnr_iob = false;

        if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
            // Might have an input buffer connected to it
            is_npnr_iob = true;
            NetInfo *o = ci->getPort(id_O);
            if (o == nullptr)
                ;
            else if (o->users.entries() > 1)
                log_error("Top level pin '%s' has multiple input buffers\n", ctx->nameOf(port.first));
            else if (o->users.entries() == 1)
                top_port = *o->users.begin();
        }
        if (ci->type == ctx->id("$nextpnr_obuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
            // Might have an output buffer connected to it
            is_npnr_iob = true;
            NetInfo *i = ci->getPort(id_I);
            if (i != nullptr && i->driver.cell != nullptr) {
                if (top_port.cell != nullptr)
                    log_error("Top level pin '%s' has multiple input/output buffers\n", ctx->nameOf(port.first));
                top_port = i->driver;
            }
            // Edge case of a bidirectional buffer driving an output pin
            if (i->users.entries() > 2) {
                log_error("Top level pin '%s' has illegal buffer configuration\n", ctx->nameOf(port.first));
            } else if (i->users.entries() == 2) {
                if (top_port.cell != nullptr)
                    log_error("Top level pin '%s' has illegal buffer configuration\n", ctx->nameOf(port.first));
                for (auto &usr : i->users) {
                    if (usr.cell->type == ctx->id("$nextpnr_obuf") || usr.cell->type == ctx->id("$nextpnr_iobuf"))
                        continue;
                    top_port = usr;
                    break;
                }
            }
        }
        if (!is_npnr_iob)
            log_error("Port '%s' doesn't seem to have a corresponding top level IO (internal cell type mismatch)\n",
                      ctx->nameOf(port.first));

        if (top_port.cell == nullptr) {
            log_info("Trimming port '%s' as it is unused.\n", ctx->nameOf(port.first));
        } else {
            // Copy attributes to real IO buffer
            for (auto &attrs : ci->attrs)
                top_port.cell->attrs[attrs.first] = attrs.second;
            for (auto &params : ci->params) {
                IdString key = params.first;
                if (top_port.cell->type.in(id_CC_LVDS_IBUF, id_CC_LVDS_OBUF, id_CC_LVDS_TOBUF, id_CC_LVDS_IOBUF)) {
                    if (top_port.port.in(id_I_P, id_O_P, id_IO_P))
                        key = id_PIN_NAME_P;
                    if (top_port.port.in(id_I_N, id_O_N, id_IO_N))
                        key = id_PIN_NAME_N;
                }
                if (top_port.cell->params.count(key)) {
                    if (top_port.cell->params[key] != params.second) {
                        std::string val = params.second.is_string ? params.second.as_string()
                                                                  : std::to_string(params.second.as_int64());
                        log_warning("Overriding parameter '%s' with value '%s' for cell '%s'.\n", key.c_str(ctx),
                                    val.c_str(), ctx->nameOf(top_port.cell));
                    }
                }
                top_port.cell->params[key] = params.second;
            }

            // Make sure that top level net is set correctly
            port.second.net = top_port.cell->ports.at(top_port.port).net;
        }
        // Now remove the nextpnr-inserted buffer
        ci->disconnectPort(id_I);
        ci->disconnectPort(id_O);
        ctx->cells.erase(port.first);
    }

    for (auto &cell : ctx->cells) {
        CellInfo &ci = *cell.second;
        if (!ci.type.in(id_CC_IBUF, id_CC_OBUF, id_CC_TOBUF, id_CC_IOBUF, id_CC_LVDS_IBUF, id_CC_LVDS_OBUF,
                        id_CC_LVDS_TOBUF, id_CC_LVDS_IOBUF))
            continue;

        bool is_lvds = ci.type.in(id_CC_LVDS_IBUF, id_CC_LVDS_OBUF, id_CC_LVDS_TOBUF, id_CC_LVDS_IOBUF);

        std::string loc = str_or_default(ci.params, is_lvds ? id_PIN_NAME_P : id_PIN_NAME, "UNPLACED");
        if (ci.params.count(id_LOC)) {
            std::string new_loc = str_or_default(ci.params, id_LOC, "UNPLACED");
            if (loc != "UNPLACED" && loc != new_loc)
                log_warning("Overriding location of cell '%s' from '%s' with '%s'\n", ctx->nameOf(&ci), loc.c_str(),
                            new_loc.c_str());
            loc = new_loc;
        }

        if (loc == "UNPLACED")
            log_warning("IO signal name '%s' is not defined in CCF file and will be auto-placed.\n", ctx->nameOf(&ci));

        disconnect_if_gnd(&ci, id_T);
        if (ci.type == id_CC_TOBUF && !ci.getPort(id_T))
            ci.type = id_CC_OBUF;
        if (ci.type == id_CC_LVDS_TOBUF && !ci.getPort(id_T))
            ci.type = id_CC_LVDS_OBUF;

        std::vector<IdString> keys;
        for (auto &p : ci.params) {

            if (p.first.in(id_PIN_NAME, id_PIN_NAME_P, id_PIN_NAME_N)) {
                if (ctx->get_package_pin_bel(ctx->id(p.second.as_string())) == BelId())
                    log_error("Unknown %s '%s' for cell '%s'.\n", p.first.c_str(ctx), p.second.as_string().c_str(),
                              ci.name.c_str(ctx));
                keys.push_back(p.first);
                continue;
            }
            if (p.first.in(id_V_IO, id_LOC)) {
                keys.push_back(p.first);
                continue;
            }
            if (ci.type.in(id_CC_IBUF, id_CC_IOBUF) &&
                p.first.in(id_PULLUP, id_PULLDOWN, id_KEEPER, id_SCHMITT_TRIGGER, id_DELAY_IBF, id_FF_IBF))
                continue;
            if (ci.type.in(id_CC_TOBUF) && p.first.in(id_PULLUP, id_PULLDOWN, id_KEEPER))
                continue;
            if (ci.type.in(id_CC_OBUF, id_CC_TOBUF, id_CC_IOBUF) &&
                p.first.in(id_DRIVE, id_SLEW, id_DELAY_OBF, id_FF_OBF))
                continue;
            if (ci.type.in(id_CC_LVDS_IBUF, id_CC_LVDS_IOBUF) && p.first.in(id_LVDS_RTERM, id_DELAY_IBF, id_FF_IBF))
                continue;
            if (ci.type.in(id_CC_LVDS_OBUF, id_CC_LVDS_TOBUF, id_CC_LVDS_IOBUF) &&
                p.first.in(id_LVDS_BOOST, id_DELAY_OBF, id_FF_OBF))
                continue;
            log_warning("Removing unsupported parameter '%s' for type '%s'.\n", p.first.c_str(ctx), ci.type.c_str(ctx));
            keys.push_back(p.first);
        }
        if (ci.params.count(id_SLEW)) {
            std::string val = str_or_default(ci.params, id_SLEW, "UNDEFINED");
            if (val == "UNDEFINED")
                keys.push_back(id_SLEW);
            else if (val == "FAST")
                ci.params[id_SLEW] = Property(Property::State::S1);
            else if (val == "SLOW")
                ci.params[id_SLEW] = Property(Property::State::S0);
            else
                log_error("Unknown value '%s' for SLEW parameter of '%s' cell.\n", val.c_str(), ci.name.c_str(ctx));
        }
        if (is_lvds) {
            std::string p_pin = str_or_default(ci.params, id_PIN_NAME_P, "UNPLACED");
            std::string n_pin = str_or_default(ci.params, id_PIN_NAME_N, "UNPLACED");
            if (p_pin == "UNPLACED" || n_pin == "UNPLACED")
                log_error("Both LVDS pins must be set to a valid locations.\n");
            if (p_pin.substr(0, 6) != n_pin.substr(0, 6) || p_pin[7] != n_pin[7])
                log_error("Both LVDS pads '%s' and '%s' do not match.\n", p_pin.c_str(), n_pin.c_str());
            if (p_pin[6] != 'A')
                log_error("Both LVDS positive pad must be from type A.\n");
            if (n_pin[6] != 'B')
                log_error("Both LVDS negative pad must be from type B.\n");
        }
        for (auto key : keys)
            ci.params.erase(key);

        if ((ci.params.count(id_KEEPER) + ci.params.count(id_PULLUP) + ci.params.count(id_PULLDOWN)) > 1)
            log_error("PULLUP, PULLDOWN and KEEPER are mutually exclusive parameters.\n");

        if (is_lvds)
            ci.params[id_LVDS_EN] = Property(Property::State::S1);

        // DELAY_IBF and DELAY_OBF must be set depending of type
        // Also we need to enable input/output
        if (ci.type.in(id_CC_IBUF, id_CC_IOBUF, id_CC_LVDS_IBUF, id_CC_LVDS_IOBUF)) {
            ci.params[id_DELAY_IBF] = Property(1 << int_or_default(ci.params, id_DELAY_IBF, 0), 16);
            if (is_lvds)
                ci.params[id_LVDS_IE] = Property(Property::State::S1);
            else
                ci.params[id_INPUT_ENABLE] = Property(Property::State::S1);
        }
        if (ci.type.in(id_CC_OBUF, id_CC_TOBUF, id_CC_IOBUF, id_CC_LVDS_OBUF, id_CC_LVDS_TOBUF, id_CC_LVDS_IOBUF)) {
            ci.params[id_DELAY_OBF] = Property(1 << int_or_default(ci.params, id_DELAY_OBF, 0), 16);
            ci.params[id_OE_ENABLE] = Property(Property::State::S1);
        }
        if (ci.params.count(id_DRIVE)) {
            int val = int_or_default(ci.params, id_DRIVE, 0);
            if (val != 3 && val != 6 && val != 9 && val != 12)
                log_error("Unsupported value '%d' for DRIVE parameter of '%s' cell.\n", val, ci.name.c_str(ctx));
            ci.params[id_DRIVE] = Property((val - 3) / 3, 2);
        }
        for (auto &p : ci.params) {
            if (p.first.in(id_PULLUP, id_PULLDOWN, id_KEEPER, id_SCHMITT_TRIGGER, id_FF_OBF, id_FF_IBF, id_LVDS_RTERM,
                           id_LVDS_BOOST)) {
                int val = int_or_default(ci.params, p.first, 0);
                if (val != 0 && val != 1)
                    log_error("Unsupported value '%d' for %s parameter of '%s' cell.\n", val, p.first.c_str(ctx),
                              ci.name.c_str(ctx));
                ci.params[p.first] = Property(val, 1);
            }
        }

        // Disconnect PADs
        ci.disconnectPort(id_IO);
        ci.disconnectPort(id_I);
        ci.disconnectPort(id_O);
        ci.disconnectPort(id_IO_P);
        ci.disconnectPort(id_IO_N);
        ci.disconnectPort(id_I_P);
        ci.disconnectPort(id_I_N);
        ci.disconnectPort(id_O_P);
        ci.disconnectPort(id_O_N);

        // Remap ports to GPIO bel
        ci.renamePort(id_A, id_DO);
        ci.renamePort(id_Y, id_DI);
        ci.renamePort(id_T, id_OE);

        NetInfo *do_net = ci.getPort(id_DO);
        if (do_net) {
            if (do_net->name.in(ctx->id("$PACKER_GND"), ctx->id("$PACKER_VCC"))) {
                ci.params[id_OUT23_14_SEL] =
                        Property(do_net->name == ctx->id("$PACKER_VCC") ? Property::State::S1 : Property::State::S0);
                ci.disconnectPort(id_DO);
            } else {
                ci.params[id_OUT_SIGNAL] = Property(Property::State::S1);
            }
        }
        if (!loc.empty()) {
            BelId bel = ctx->get_package_pin_bel(ctx->id(loc));
            if (bel == BelId())
                log_error("Unable to constrain IO '%s', device does not have a pin named '%s'\n", ci.name.c_str(ctx),
                          loc.c_str());
            log_info("    Constraining '%s' to pad '%s'\n", ci.name.c_str(ctx), loc.c_str());
            if (!ctx->checkBelAvail(bel)) {
                log_error("Can't place %s at %s because it's already taken by %s\n", ctx->nameOf(&ci),
                          ctx->nameOfBel(bel), ctx->nameOf(ctx->getBoundBelCell(bel)));
            }
            ctx->bindBel(bel, &ci, PlaceStrength::STRENGTH_FIXED);
        }
    }
}

void GateMatePacker::pack_cpe()
{
    log_info("Packing CPEs..\n");
    for (auto &cell : ctx->cells) {
        CellInfo &ci = *cell.second;
        if (!ci.type.in(id_CC_L2T4, id_CC_L2T5, id_CC_LUT2, id_CC_LUT1))
            continue;
        if (ci.type == id_CC_L2T5) {
            ci.renamePort(id_I0, id_IN5);
            ci.renamePort(id_I1, id_IN6);
            ci.renamePort(id_I2, id_IN7);
            ci.renamePort(id_I3, id_IN8);

            ci.renamePort(id_I4, id_IN1);
            ci.renamePort(id_O, id_OUT1);
            ci.params[id_INIT_L00] = Property(0b1010, 4);
            ci.params[id_INIT_L10] = Property(0b1010, 4);
            ci.params[id_O1] = Property(0b11, 2);
        } else {
            ci.renamePort(id_I0, id_IN1);
            ci.renamePort(id_I1, id_IN2);
            ci.renamePort(id_I2, id_IN3);
            ci.renamePort(id_I3, id_IN4);
            ci.renamePort(id_O, id_OUT1);
            ci.params[id_O1] = Property(0b11, 2);
            ci.params[id_INIT_L20] = Property(0b1010, 4);
            if (ci.type.in(id_CC_LUT1, id_CC_LUT2)) {
                uint8_t val = int_or_default(ci.params, id_INIT, 0);
                if (ci.type == id_CC_LUT1)
                    val = val << 2 | val;
                ci.params[id_INIT_L00] = Property(val, 4);
                ci.unsetParam(id_INIT);
                ci.params[id_INIT_L10] = Property(0b1010, 4);
            }
        }
        ci.type = id_CPE;
    }

    for (auto &cell : ctx->cells) {
        CellInfo &ci = *cell.second;
        if (!ci.type.in(id_CC_MX2, id_CC_MX4))
            continue;

        ci.renamePort(id_D0, id_IN1);
        ci.renamePort(id_D1, id_IN2);
        ci.renamePort(id_S0, id_IN6);
        ci.renamePort(id_Y, id_OUT1);
        // Only for CC_MX4
        ci.renamePort(id_D2, id_IN3);
        ci.renamePort(id_D3, id_IN4);
        ci.renamePort(id_S1, id_IN8);

        uint8_t select = 0;
        uint8_t invert = 0;
        for(int i=0;i<4;i++) {
            NetInfo *net = ci.getPort(ctx->idf("IN%d",i+1));
            if (net) {
                if (net->name.in(ctx->id("$PACKER_GND"),ctx->id("$PACKER_VCC"))) {
                    if (net->name == ctx->id("$PACKER_VCC"))
                        invert |= 1<< i;
                    ci.disconnectPort(ctx->idf("IN%d",i+1));
                } else {
                    select |= 1 << i;
                }
            }
        }
        ci.params[id_FUNCTION] = Property(0b100, 3);
        ci.params[id_INIT_L02] = Property(0b1100, 4); // IN6
        if (ci.type == id_CC_MX4)
            ci.params[id_INIT_L03] = Property(0b1100, 4); // IN8
        ci.params[id_INIT_L10] = Property(select, 4); // Selection bits
        ci.params[id_INIT_L11] = Property(invert, 4); // Inversion bits
        ci.params[id_INIT_L20] = Property(0b1100, 4); // Always D1
        ci.params[id_O1] = Property(0b11, 2);
        ci.type = id_CPE;
    }

    for (auto &cell : ctx->cells) {
        CellInfo &ci = *cell.second;
        if (!ci.type.in(id_CC_DFF))
            continue;
        ci.renamePort(id_Q, id_OUT2);
        ci.params[id_O2] = Property(0b00, 2);
        ci.params[id_2D_IN] = Property(1, 1);
        NetInfo *d_net = ci.getPort(id_D);
        if (d_net->name == ctx->id("$PACKER_GND")) {
            ci.params[id_INIT_L00] = Property(0b0000, 4);
            ci.disconnectPort(id_D);
        } else if (d_net->name == ctx->id("$PACKER_VCC")) {
            ci.params[id_INIT_L00] = Property(0b1111, 4);
            ci.disconnectPort(id_D);
        } else {
            ci.params[id_INIT_L00] = Property(0b1010, 4);
        }
        ci.params[id_INIT_L10] = Property(0b1010, 4);
        ci.renamePort(id_D, id_IN1);

        NetInfo *en_net = ci.getPort(id_EN);
        bool invert = int_or_default(ci.params, id_EN_INV, 0) == 1;
        if (en_net) {
            if (en_net->name == ctx->id("$PACKER_GND")) {
                ci.params[id_EN] = Property(invert ? 0b11 : 0b00, 2);
                ci.disconnectPort(id_EN);
            } else if (en_net->name == ctx->id("$PACKER_VCC")) {
                ci.params[id_EN] = Property(invert ? 0b00 : 0b11, 2);
                ci.disconnectPort(id_EN);
            } else {
                ci.params[id_EN] = Property(invert ? 0b01 : 0b10, 2);
            }
        } else {
            ci.params[id_EN] = Property(invert ? 0b11 : 0b00, 2);
        }
        ci.unsetParam(id_EN_INV);

        NetInfo *clk_net = ci.getPort(id_CLK);
        invert = int_or_default(ci.params, id_CLK_INV, 0) == 1;
        if (clk_net) {
            if (clk_net->name == ctx->id("$PACKER_GND")) {
                ci.params[id_CLK] = Property(invert ? 0b11 : 0b00, 2);
                ci.disconnectPort(id_CLK);
            } else if (clk_net->name == ctx->id("$PACKER_VCC")) {
                ci.params[id_CLK] = Property(invert ? 0b00 : 0b11, 2);
                ci.disconnectPort(id_CLK);
            } else {
                ci.params[id_CLK] = Property(invert ? 0b01 : 0b10, 2);
            }
        } else {
            ci.params[id_CLK] = Property(invert ? 0b11 : 0b00, 2);
        }
        ci.unsetParam(id_CLK_INV);

        NetInfo *sr_net = ci.getPort(id_SR);
        invert = int_or_default(ci.params, id_SR_INV, 0) == 1;
        int  sr_val = int_or_default(ci.params, id_SR_VAL, 0) == 1;
        if (sr_net) {
            if (sr_net->name == ctx->id("$PACKER_GND")) {
                if (invert)
                    log_error("Invalid DFF configuration\n.");
                ci.params[id_R] = Property(0b11, 2);
                ci.params[id_S] = Property(0b11, 2);
                ci.disconnectPort(id_SR);
            } else if (sr_net->name == ctx->id("$PACKER_VCC")) {
                if (!invert)
                    log_error("Invalid DFF configuration\n.");
                ci.params[id_R] = Property(0b11, 2);
                ci.params[id_S] = Property(0b11, 2);
                ci.disconnectPort(id_SR);
            } else {
                if (sr_val) {
                    ci.params[id_R] = Property(0b11, 2);
                    ci.params[id_S] = Property(invert ? 0b01 : 0b10, 2);
                    ci.params[id_EN_SR] = Property(0b1, 1);
                } else {
                    ci.params[id_R] = Property(invert ? 0b01 : 0b10, 2);
                    ci.params[id_S] = Property(0b11, 2);
                }
            }
        } else {
            if (invert)
                log_error("Invalid DFF configuration\n.");
            ci.params[id_R] = Property(0b11, 2);
            ci.params[id_S] = Property(0b11, 2);
        }
        ci.unsetParam(id_SR_VAL);
        ci.unsetParam(id_SR_INV);

        if (ci.params.count(id_INIT) && ci.params[id_INIT].is_fully_def()) {
            bool init = int_or_default(ci.params, id_INIT, 0) == 1;
            if (init)
                ci.params[id_FF_INIT] = Property(0b11, 2);
            else
                ci.params[id_FF_INIT] = Property(0b10, 2);
            ci.unsetParam(id_INIT);
        } else {
            ci.unsetParam(id_INIT);
        }
        ci.type = id_CPE;
    }
}

void GateMatePacker::pack_bufg()
{
    log_info("Packing BUFGs..\n");
    for (auto &cell : ctx->cells) {
        CellInfo &ci = *cell.second;
        if (!ci.type.in(id_CC_BUFG))
            continue;
        ci.type = id_BUFG;
    }
}

template <typename KeyType> double double_or_default(const dict<KeyType, Property> &ct, const KeyType &key, double def = 0)
{
    auto found = ct.find(key);
    if (found == ct.end())
        return def;
    else {
        if (found->second.is_string) {
            try {
                return std::stod(found->second.as_string());
            } catch (std::invalid_argument &e) {
                log_error("Expecting numeric value but got '%s'.\n", found->second.as_string().c_str());
            }
        } else
            return double(found->second.as_int64());
    }
};

void GateMatePacker::pack_pll()
{
    log_info("Packing PLLss..\n");
    for (auto &cell : ctx->cells) {
        CellInfo &ci = *cell.second;
        if (!ci.type.in(id_CC_PLL))
            continue;

        disconnect_if_gnd(&ci, id_CLK_REF);
        disconnect_if_gnd(&ci, id_USR_CLK_REF);
        disconnect_if_gnd(&ci, id_CLK_FEEDBACK);
        disconnect_if_gnd(&ci, id_USR_LOCKED_STDY_RST);

        ci.params[id_LOCK_REQ] = Property(int_or_default(ci.params, id_LOCK_REQ, 1),1);
        ci.params[id_CLK180_DOUB] = Property(int_or_default(ci.params, id_CLK180_DOUB, 0),1);
        ci.params[id_CLK270_DOUB] = Property(int_or_default(ci.params, id_CLK270_DOUB, 0),1);
        std::string mode = str_or_default(ci.params, id_PERF_MD, "SPEED");
        boost::algorithm::to_upper(mode);
        int perf_md;
        if (mode == "LOWPOWER") perf_md = 1;
        else if (mode == "ECONOMY") perf_md = 2;
        else if (mode == "SPEED") perf_md = 3;
        else log_error("Unknown PERF_MD parameter value '%s' for cell %s.\n", mode.c_str(), ci.name.c_str(ctx));


        double ref_clk = double_or_default(ci.params, id_REF_CLK, 0.0);
        if (ref_clk <= 0 || ref_clk > 125)
            log_error("REF_CLK parameter is out of range (0,125.00].\n");

        double max_freq = 0.0;
        switch(perf_md) {
            case 1: max_freq = 250.00; break;
            case 2: max_freq = 312.50; break;
            case 3: max_freq = 416.75; break;
        }

        double out_clk = double_or_default(ci.params, id_OUT_CLK, 0.0);
        if (out_clk <= 0 || out_clk > max_freq)
            log_error("OUT_CLK parameter is out of range (0,%.2lf].\n", max_freq);

        // For 10 MHz - > 25 MHz
        ci.params[ctx->id("CFG_A.AO_SW")] = Property(0b01000,5);
        ci.params[ctx->id("CFG_A.CI_FILTER_CONST")] = Property(0b00010,5);
        ci.params[ctx->id("CFG_A.COARSE_TUNE")] = Property(0b100,3);
        ci.params[ctx->id("CFG_A.CP_FILTER_CONST")] = Property(0b00100,5);
        ci.params[ctx->id("CFG_A.EN_COARSE_TUNE")] = Property(0b1,1);
        ci.params[ctx->id("CFG_A.FAST_LOCK")] = Property(0b1,1);
        ci.params[ctx->id("CFG_A.FILTER_SHIFT")] = Property(0b10,2);
        ci.params[ctx->id("CFG_A.FINE_TUNE")] = Property(0b00011001000,11);
        ci.params[ctx->id("CFG_A.K")] = Property(0b000000000001,12);
        ci.params[ctx->id("CFG_A.M1")] = Property(0b000010,6);
        ci.params[ctx->id("CFG_A.M2")] = Property(0b0000001001,10);
        ci.params[ctx->id("CFG_A.N1")] = Property(0b001001,6);
        ci.params[ctx->id("CFG_A.N2")] = Property(0b0000001010,10);
        ci.params[ctx->id("CFG_A.PDIV0_MUX")] = Property(0b1,1);
        ci.params[ctx->id("CFG_A.PDIV1_SEL")] = Property(0b1,1);
        ci.params[ctx->id("CFG_A.SAR_LIMIT")] = Property(0b010,3);

        // Remove all not propagated parameters
        ci.unsetParam(id_PERF_MD);
        ci.unsetParam(id_REF_CLK);
        ci.unsetParam(id_OUT_CLK);        
        ci.unsetParam(id_LOW_JITTER);
        ci.unsetParam(id_CI_FILTER_CONST);
        ci.unsetParam(id_CP_FILTER_CONST);
        //ci.unsetParam(id_PLL_CFG_A);
        //ci.unsetParam(id_PLL_CFG_B);

        ci.type = id_PLL;
    }
}
void GateMatePacker::pack_constants()
{
    log_info("Packing constants..\n");
    // Replace constants with LUTs
    const dict<IdString, Property> vcc_params = {{id_INIT_L20, Property(0b1111, 4)}, {id_O1, Property(0b11, 2)}};
    const dict<IdString, Property> gnd_params = {{id_INIT_L20, Property(0b0000, 4)}, {id_O1, Property(0b11, 2)}};

    h.replace_constants(CellTypePort(id_CPE, id_OUT1), CellTypePort(id_CPE, id_OUT1), vcc_params, gnd_params);
}

void GateMatePacker::remove_constants()
{
    log_info("Removing constants..\n");
    auto fnd_cell = ctx->cells.find(ctx->id("$PACKER_VCC_DRV"));
    if (fnd_cell != ctx->cells.end()) {
        auto fnd_net = ctx->nets.find(ctx->id("$PACKER_VCC"));
        if (fnd_net != ctx->nets.end() && fnd_net->second->users.entries() == 0) {
            BelId bel = (*fnd_cell).second.get()->bel;
            if (bel != BelId())
                ctx->unbindBel(bel);
            ctx->cells.erase(fnd_cell);
            ctx->nets.erase(fnd_net);
            log_info("    Removed unused VCC cell\n");
        }
    }
    fnd_cell = ctx->cells.find(ctx->id("$PACKER_GND_DRV"));
    if (fnd_cell != ctx->cells.end()) {
        auto fnd_net = ctx->nets.find(ctx->id("$PACKER_GND"));
        if (fnd_net != ctx->nets.end() && fnd_net->second->users.entries() == 0) {
            BelId bel = (*fnd_cell).second.get()->bel;
            if (bel != BelId())
                ctx->unbindBel(bel);
            ctx->cells.erase(fnd_cell);
            ctx->nets.erase(fnd_net);
            log_info("    Removed unused GND cell\n");
        }
    }
}

void GateMateImpl::pack()
{
    const ArchArgs &args = ctx->args;
    if (args.options.count("ccf")) {
        parse_ccf(args.options.at("ccf"));
    }

    GateMatePacker packer(ctx, this);
    packer.pack_constants();
    packer.pack_io();
    packer.pack_pll();
    packer.pack_bufg();
    packer.pack_cpe();
    packer.remove_constants();
}

NEXTPNR_NAMESPACE_END