335 lines
11 KiB
C++
335 lines
11 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2019 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "nextpnr.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace SDF {
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struct MinMaxTyp
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{
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double min, typ, max;
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};
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struct RiseFallDelay
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{
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MinMaxTyp rise, fall;
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};
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struct PortAndEdge
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{
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std::string port;
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ClockEdge edge;
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};
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struct IOPath
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{
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std::string from, to;
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RiseFallDelay delay;
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};
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struct TimingCheck
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{
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enum CheckType
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{
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SETUPHOLD,
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PERIOD,
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WIDTH
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} type;
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PortAndEdge from, to;
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RiseFallDelay delay;
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};
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struct Cell
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{
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std::string celltype, instance;
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std::vector<IOPath> iopaths;
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std::vector<TimingCheck> checks;
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};
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struct CellPort
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{
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std::string cell, port;
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};
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struct Interconnect
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{
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CellPort from, to;
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RiseFallDelay delay;
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};
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struct SDFWriter
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{
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bool cvc_mode = false;
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std::vector<Cell> cells;
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std::vector<Interconnect> conn;
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std::string sdfversion, design, vendor, program;
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std::string format_name(const std::string &name)
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{
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std::string fmt = "\"";
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for (char c : name) {
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if (c == '\\' || c == '\"')
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fmt += "\"";
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fmt += c;
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}
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fmt += "\"";
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return fmt;
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}
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std::string escape_name(const std::string &name)
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{
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std::string esc;
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for (char c : name) {
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if (c == '$' || c == '\\' || c == '[' || c == ']' || c == ':' || (cvc_mode && c == '.'))
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esc += '\\';
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esc += c;
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}
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return esc;
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}
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std::string timing_check_name(TimingCheck::CheckType type)
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{
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switch (type) {
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case TimingCheck::SETUPHOLD:
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return "SETUPHOLD";
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case TimingCheck::PERIOD:
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return "PERIOD";
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case TimingCheck::WIDTH:
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return "WIDTH";
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default:
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NPNR_ASSERT_FALSE("unknown timing check type");
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}
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}
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void write_delay(std::ostream &out, const RiseFallDelay &delay)
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{
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write_delay(out, delay.rise);
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out << " ";
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write_delay(out, delay.fall);
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}
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void write_delay(std::ostream &out, const MinMaxTyp &delay)
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{
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if (cvc_mode)
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out << "(" << int(delay.min) << ":" << int(delay.typ) << ":" << int(delay.max) << ")";
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else
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out << "(" << delay.min << ":" << delay.typ << ":" << delay.max << ")";
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}
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void write_port(std::ostream &out, const CellPort &port)
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{
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if (cvc_mode)
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out << escape_name(port.cell) + "." + escape_name(port.port);
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else
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out << escape_name(port.cell + "/" + port.port);
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}
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void write_portedge(std::ostream &out, const PortAndEdge &pe)
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{
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out << "(" << (pe.edge == RISING_EDGE ? "posedge" : "negedge") << " " << escape_name(pe.port) << ")";
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}
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void write(std::ostream &out)
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{
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out << "(DELAYFILE" << std::endl;
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// Headers and metadata
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out << " (SDFVERSION " << format_name(sdfversion) << ")" << std::endl;
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out << " (DESIGN " << format_name(design) << ")" << std::endl;
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out << " (VENDOR " << format_name(vendor) << ")" << std::endl;
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out << " (PROGRAM " << format_name(program) << ")" << std::endl;
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out << " (DIVIDER " << (cvc_mode ? "." : "/") << ")" << std::endl;
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out << " (TIMESCALE 1ps)" << std::endl;
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// Write interconnect delays, with the main design begin a "cell"
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out << " (CELL" << std::endl;
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out << " (CELLTYPE " << format_name(design) << ")" << std::endl;
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out << " (INSTANCE )" << std::endl;
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out << " (DELAY" << std::endl;
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out << " (ABSOLUTE" << std::endl;
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for (auto &ic : conn) {
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out << " (INTERCONNECT ";
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write_port(out, ic.from);
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out << " ";
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write_port(out, ic.to);
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out << " ";
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write_delay(out, ic.delay);
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out << ")" << std::endl;
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}
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out << " )" << std::endl;
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out << " )" << std::endl;
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out << " )" << std::endl;
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// Write cells
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for (auto &cell : cells) {
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out << " (CELL" << std::endl;
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out << " (CELLTYPE " << format_name(cell.celltype) << ")" << std::endl;
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out << " (INSTANCE " << escape_name(cell.instance) << ")" << std::endl;
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// IOPATHs (combinational delay and clock-to-q)
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if (!cell.iopaths.empty()) {
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out << " (DELAY" << std::endl;
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out << " (ABSOLUTE" << std::endl;
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for (auto &path : cell.iopaths) {
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out << " (IOPATH " << escape_name(path.from) << " " << escape_name(path.to) << " ";
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write_delay(out, path.delay);
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out << ")" << std::endl;
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}
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out << " )" << std::endl;
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out << " )" << std::endl;
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}
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// Timing Checks (setup/hold, period, width)
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if (!cell.checks.empty()) {
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out << " (TIMINGCHECK" << std::endl;
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for (auto &check : cell.checks) {
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out << " (" << timing_check_name(check.type) << " ";
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write_portedge(out, check.from);
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out << " ";
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if (check.type == TimingCheck::SETUPHOLD) {
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write_portedge(out, check.to);
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out << " ";
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}
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if (check.type == TimingCheck::SETUPHOLD)
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write_delay(out, check.delay);
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else
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write_delay(out, check.delay.rise);
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out << ")" << std::endl;
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}
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out << " )" << std::endl;
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}
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out << " )" << std::endl;
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}
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out << ")" << std::endl;
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}
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};
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} // namespace SDF
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void Context::writeSDF(std::ostream &out, bool cvc_mode) const
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{
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using namespace SDF;
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SDFWriter wr;
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wr.cvc_mode = cvc_mode;
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wr.design = str_or_default(attrs, id("module"), "top");
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wr.sdfversion = "3.0";
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wr.vendor = "nextpnr";
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wr.program = "nextpnr";
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const double delay_scale = 1000;
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// Convert from DelayQuad to SDF-friendly RiseFallDelay
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auto convert_delay = [&](const DelayQuad &dly) {
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RiseFallDelay rf;
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rf.rise.min = getDelayNS(dly.minRiseDelay()) * delay_scale;
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rf.rise.typ = getDelayNS((dly.minRiseDelay() + dly.maxRiseDelay()) / 2) * delay_scale; // fixme: typ delays?
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rf.rise.max = getDelayNS(dly.maxRiseDelay()) * delay_scale;
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rf.fall.min = getDelayNS(dly.minFallDelay()) * delay_scale;
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rf.fall.typ = getDelayNS((dly.minFallDelay() + dly.maxFallDelay()) / 2) * delay_scale; // fixme: typ delays?
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rf.fall.max = getDelayNS(dly.maxFallDelay()) * delay_scale;
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return rf;
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};
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auto convert_setuphold = [&](const DelayPair &setup, const DelayPair &hold) {
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RiseFallDelay rf;
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rf.rise.min = getDelayNS(setup.minDelay()) * delay_scale;
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rf.rise.typ = getDelayNS((setup.minDelay() + setup.maxDelay()) / 2) * delay_scale; // fixme: typ delays?
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rf.rise.max = getDelayNS(setup.maxDelay()) * delay_scale;
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rf.fall.min = getDelayNS(hold.minDelay()) * delay_scale;
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rf.fall.typ = getDelayNS((hold.minDelay() + hold.maxDelay()) / 2) * delay_scale; // fixme: typ delays?
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rf.fall.max = getDelayNS(hold.maxDelay()) * delay_scale;
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return rf;
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};
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for (const auto &cell : cells) {
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Cell sc;
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const CellInfo *ci = cell.second.get();
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sc.instance = ci->name.str(this);
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sc.celltype = ci->type.str(this);
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for (auto port : ci->ports) {
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int clockCount = 0;
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TimingPortClass cls = getPortTimingClass(ci, port.first, clockCount);
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if (cls == TMG_IGNORE)
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continue;
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if (port.second.net == nullptr)
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continue; // Ignore disconnected ports
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if (port.second.type != PORT_IN) {
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// Add combinational paths to this output (or inout)
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for (auto other : ci->ports) {
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if (other.second.net == nullptr)
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continue;
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if (other.second.type == PORT_OUT)
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continue;
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DelayQuad dly;
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if (!getCellDelay(ci, other.first, port.first, dly))
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continue;
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IOPath iop;
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iop.from = other.first.str(this);
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iop.to = port.first.str(this);
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iop.delay = convert_delay(dly);
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sc.iopaths.push_back(iop);
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}
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// Add clock-to-output delays, also as IOPaths
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if (cls == TMG_REGISTER_OUTPUT)
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for (int i = 0; i < clockCount; i++) {
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auto clkInfo = getPortClockingInfo(ci, port.first, i);
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IOPath cqp;
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cqp.from = clkInfo.clock_port.str(this);
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cqp.to = port.first.str(this);
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cqp.delay = convert_delay(clkInfo.clockToQ);
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sc.iopaths.push_back(cqp);
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}
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}
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if (port.second.type != PORT_OUT && cls == TMG_REGISTER_INPUT) {
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// Add setup/hold checks
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for (int i = 0; i < clockCount; i++) {
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auto clkInfo = getPortClockingInfo(ci, port.first, i);
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TimingCheck chk;
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chk.from.edge = RISING_EDGE; // Add setup/hold checks equally for rising and falling edges
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chk.from.port = port.first.str(this);
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chk.to.edge = clkInfo.edge;
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chk.to.port = clkInfo.clock_port.str(this);
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chk.type = TimingCheck::SETUPHOLD;
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chk.delay = convert_setuphold(clkInfo.setup, clkInfo.hold);
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sc.checks.push_back(chk);
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chk.from.edge = FALLING_EDGE;
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sc.checks.push_back(chk);
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}
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}
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}
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wr.cells.push_back(sc);
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}
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for (auto &net : nets) {
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NetInfo *ni = net.second.get();
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if (ni->driver.cell == nullptr)
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continue;
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for (auto &usr : ni->users) {
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Interconnect ic;
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ic.from.cell = ni->driver.cell->name.str(this);
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ic.from.port = ni->driver.port.str(this);
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ic.to.cell = usr.cell->name.str(this);
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ic.to.port = usr.port.str(this);
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// FIXME: min/max routing delay
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ic.delay = convert_delay(getNetinfoRouteDelayQuad(ni, usr));
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wr.conn.push_back(ic);
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}
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}
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wr.write(out);
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}
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NEXTPNR_NAMESPACE_END
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