71 lines
2.4 KiB
C++
71 lines
2.4 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2022-23 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*
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*/
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#ifndef PLACER_STATIC_H
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#define PLACER_STATIC_H
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#include "log.h"
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#include "nextpnr.h"
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NEXTPNR_NAMESPACE_BEGIN
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struct StaticRect
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{
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StaticRect() : w(0), h(0) {};
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StaticRect(float w, float h) : w(w), h(h) {};
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float w, h;
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float area() const { return w * h; }
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};
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struct StaticCellGroupCfg
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{
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// name of the group for debugging purposes
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IdString name;
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// bel buckets in this group
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pool<BelBucketId> bel_buckets;
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// cell & bel types in this group and the (normalised) area of that cell/bel type
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dict<IdString, StaticRect> cell_area, bel_area;
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// these cells (generally auxilliary CLB cells like RAMW; carry; MUX) are considered to have zero area when part of
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// a macro with other non-zero-area cells
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pool<IdString> zero_area_cells;
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// size of spacers to insert
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StaticRect spacer_rect{0.5, 0.5};
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};
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struct PlacerStaticCfg
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{
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PlacerStaticCfg(Context *ctx);
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// These cell types will be randomly locked to prevent singular matrices
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pool<IdString> ioBufTypes;
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int hpwl_scale_x = 1;
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int hpwl_scale_y = 1;
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bool timing_driven = false;
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// for calculating timing estimates based on distance
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// estimate = c + mx*dx + my * dy
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delay_t timing_c = 100, timing_mx = 100, timing_my = 100;
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// groups of cells that should be placed together.
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// groups < logic_groups are logic like LUTs and FFs, further groups for BRAM/DSP/misc
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std::vector<StaticCellGroupCfg> cell_groups;
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int logic_groups = 2;
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};
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extern bool placer_static(Context *ctx, PlacerStaticCfg cfg);
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NEXTPNR_NAMESPACE_END
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#endif |