407 lines
16 KiB
C++
407 lines
16 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef GENERIC_ARCH_H
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#define GENERIC_ARCH_H
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#include <map>
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#include "arch_api.h"
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#include "base_arch.h"
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#include "idstring.h"
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#include "idstringlist.h"
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#include "nextpnr_namespaces.h"
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#include "nextpnr_types.h"
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#include "viaduct_api.h"
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NEXTPNR_NAMESPACE_BEGIN
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struct ArchArgs
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{
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// Number of LUT inputs
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int K = 4;
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// y = mx + c relationship between distance and delay for interconnect
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// delay estimates
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double delayScale = 0.1, delayOffset = 0;
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};
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struct WireInfo;
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struct PipInfo
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{
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IdStringList name;
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IdString type;
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std::map<IdString, std::string> attrs;
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NetInfo *bound_net;
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WireId srcWire, dstWire;
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delay_t delay;
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DecalXY decalxy;
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Loc loc;
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};
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struct WireInfo
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{
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IdStringList name;
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IdString type;
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std::map<IdString, std::string> attrs;
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NetInfo *bound_net;
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std::vector<PipId> downhill, uphill;
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std::vector<BelPin> bel_pins;
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DecalXY decalxy;
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int x, y;
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};
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struct PinInfo
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{
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IdString name;
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WireId wire;
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PortType type;
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};
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struct BelInfo
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{
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IdStringList name;
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IdString type;
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std::map<IdString, std::string> attrs;
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CellInfo *bound_cell;
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dict<IdString, PinInfo> pins;
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DecalXY decalxy;
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int x, y, z;
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bool gb;
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bool hidden;
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};
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struct GroupInfo
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{
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IdStringList name;
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std::vector<BelId> bels;
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std::vector<WireId> wires;
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std::vector<PipId> pips;
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std::vector<GroupId> groups;
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DecalXY decalxy;
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};
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struct CellDelayKey
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{
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IdString from, to;
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inline bool operator==(const CellDelayKey &other) const { return from == other.from && to == other.to; }
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unsigned int hash() const { return mkhash(from.hash(), to.hash()); }
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};
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struct CellTiming
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{
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dict<IdString, TimingPortClass> portClasses;
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dict<CellDelayKey, DelayQuad> combDelays;
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dict<IdString, std::vector<TimingClockingInfo>> clockingInfo;
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};
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template <typename TId> struct linear_range
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{
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struct iterator
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{
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explicit iterator(int32_t index) : index(index) {};
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int32_t index;
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bool operator==(const iterator &other) const { return index == other.index; }
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bool operator!=(const iterator &other) const { return index != other.index; }
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void operator++() { ++index; }
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TId operator*() const { return TId(index); }
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};
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explicit linear_range(int32_t size) : size(size) {};
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int32_t size;
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iterator begin() const { return iterator(0); }
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iterator end() const { return iterator(size); }
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};
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struct ArchRanges : BaseArchRanges
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{
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using ArchArgsT = ArchArgs;
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// Bels
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using AllBelsRangeT = linear_range<BelId>;
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using TileBelsRangeT = const std::vector<BelId> &;
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using BelAttrsRangeT = const std::map<IdString, std::string> &;
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using BelPinsRangeT = std::vector<IdString>;
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using CellBelPinRangeT = const std::vector<IdString> &;
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// Wires
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using AllWiresRangeT = linear_range<WireId>;
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using DownhillPipRangeT = const std::vector<PipId> &;
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using UphillPipRangeT = const std::vector<PipId> &;
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using WireBelPinRangeT = const std::vector<BelPin> &;
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using WireAttrsRangeT = const std::map<IdString, std::string> &;
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// Pips
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using AllPipsRangeT = linear_range<PipId>;
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using PipAttrsRangeT = const std::map<IdString, std::string> &;
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// Groups
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using AllGroupsRangeT = std::vector<GroupId>;
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using GroupBelsRangeT = const std::vector<BelId> &;
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using GroupWiresRangeT = const std::vector<WireId> &;
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using GroupPipsRangeT = const std::vector<PipId> &;
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using GroupGroupsRangeT = const std::vector<GroupId> &;
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// Decals
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using DecalGfxRangeT = const std::vector<GraphicElement> &;
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// Placement validity
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using CellTypeRangeT = std::vector<IdString>;
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using BelBucketRangeT = std::vector<BelBucketId>;
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using BucketBelRangeT = std::vector<BelId>;
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};
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struct Arch : BaseArch<ArchRanges>
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{
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std::string chipName;
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std::unique_ptr<ViaductAPI> uarch{};
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std::vector<WireInfo> wires;
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std::vector<PipInfo> pips;
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std::vector<BelInfo> bels;
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dict<GroupId, GroupInfo> groups;
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WireInfo &wire_info(WireId wire) { return wires.at(wire.index); }
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PipInfo &pip_info(PipId pip) { return pips.at(pip.index); }
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BelInfo &bel_info(BelId bel) { return bels.at(bel.index); }
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const WireInfo &wire_info(WireId wire) const { return wires.at(wire.index); }
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const PipInfo &pip_info(PipId pip) const { return pips.at(pip.index); }
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const BelInfo &bel_info(BelId bel) const { return bels.at(bel.index); }
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dict<IdStringList, WireId> wire_by_name;
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dict<IdStringList, PipId> pip_by_name;
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dict<IdStringList, BelId> bel_by_name;
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dict<Loc, BelId> bel_by_loc;
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std::vector<std::vector<std::vector<BelId>>> bels_by_tile;
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dict<DecalId, std::vector<GraphicElement>> decal_graphics;
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int gridDimX, gridDimY;
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std::vector<std::vector<int>> tileBelDimZ;
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std::vector<std::vector<int>> tilePipDimZ;
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dict<IdString, CellTiming> cellTiming;
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WireId addWire(IdStringList name, IdString type, int x, int y);
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PipId addPip(IdStringList name, IdString type, WireId srcWire, WireId dstWire, delay_t delay, Loc loc);
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BelId addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidden);
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void addBelInput(BelId bel, IdString name, WireId wire);
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void addBelOutput(BelId bel, IdString name, WireId wire);
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void addBelInout(BelId bel, IdString name, WireId wire);
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void addBelPin(BelId bel, IdString name, WireId wire, PortType type);
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WireId addWireAsBelInput(BelId bel, IdString name);
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WireId addWireAsBelOutput(BelId bel, IdString name);
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WireId addWireAsBelInout(BelId bel, IdString name);
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void addGroupBel(IdStringList group, BelId bel);
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void addGroupWire(IdStringList group, WireId wire);
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void addGroupPip(IdStringList group, PipId pip);
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void addGroupGroup(IdStringList group, IdStringList grp);
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void addDecalGraphic(IdStringList decal, const GraphicElement &graphic);
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void setWireDecal(WireId wire, float x, float y, IdStringList decal);
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void setPipDecal(PipId pip, float x, float y, IdStringList decal);
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void setBelDecal(BelId bel, float x, float y, IdStringList decal);
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void setGroupDecal(GroupId group, float x, float y, IdStringList decal);
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void setWireAttr(WireId wire, IdString key, const std::string &value);
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void setPipAttr(PipId pip, IdString key, const std::string &value);
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void setBelAttr(BelId bel, IdString key, const std::string &value);
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void setLutK(int K);
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void setDelayScaling(double scale, double offset);
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void addCellTimingClock(IdString cell, IdString port);
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void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, delay_t delay);
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void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, delay_t setup, delay_t hold);
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void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, delay_t clktoq);
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void clearCellBelPinMap(IdString cell, IdString cell_pin);
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void addCellBelPinMapping(IdString cell, IdString cell_pin, IdString bel_pin);
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// ---------------------------------------------------------------
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// Common Arch API. Every arch must provide the following methods.
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ArchArgs args;
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Arch(ArchArgs args);
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std::string getChipName() const override { return chipName; }
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IdString archId() const override { return id("generic"); }
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ArchArgs archArgs() const override { return args; }
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IdString archArgsToId(ArchArgs args) const override { return id("none"); }
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int getGridDimX() const override { return gridDimX; }
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int getGridDimY() const override { return gridDimY; }
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int getTileBelDimZ(int x, int y) const override { return tileBelDimZ[x][y]; }
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int getTilePipDimZ(int x, int y) const override { return tilePipDimZ[x][y]; }
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char getNameDelimiter() const override { return '/'; }
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BelId getBelByName(IdStringList name) const override;
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IdStringList getBelName(BelId bel) const override;
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Loc getBelLocation(BelId bel) const override;
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BelId getBelByLocation(Loc loc) const override;
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const std::vector<BelId> &getBelsByTile(int x, int y) const override;
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bool getBelGlobalBuf(BelId bel) const override;
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uint32_t getBelChecksum(BelId bel) const override;
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void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength) override;
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void unbindBel(BelId bel) override;
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bool checkBelAvail(BelId bel) const override;
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CellInfo *getBoundBelCell(BelId bel) const override;
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CellInfo *getConflictingBelCell(BelId bel) const override;
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linear_range<BelId> getBels() const override;
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IdString getBelType(BelId bel) const override;
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bool getBelHidden(BelId bel) const override;
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const std::map<IdString, std::string> &getBelAttrs(BelId bel) const override;
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WireId getBelPinWire(BelId bel, IdString pin) const override;
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PortType getBelPinType(BelId bel, IdString pin) const override;
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std::vector<IdString> getBelPins(BelId bel) const override;
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const std::vector<IdString> &getBelPinsForCellPin(const CellInfo *cell_info, IdString pin) const override;
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WireId getWireByName(IdStringList name) const override;
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IdStringList getWireName(WireId wire) const override;
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IdString getWireType(WireId wire) const override;
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const std::map<IdString, std::string> &getWireAttrs(WireId wire) const override;
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uint32_t getWireChecksum(WireId wire) const override;
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void bindWire(WireId wire, NetInfo *net, PlaceStrength strength) override;
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void unbindWire(WireId wire) override;
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bool checkWireAvail(WireId wire) const override;
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NetInfo *getBoundWireNet(WireId wire) const override;
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WireId getConflictingWireWire(WireId wire) const override { return wire; }
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NetInfo *getConflictingWireNet(WireId wire) const override;
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DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0); }
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linear_range<WireId> getWires() const override;
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const std::vector<BelPin> &getWireBelPins(WireId wire) const override;
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PipId getPipByName(IdStringList name) const override;
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IdStringList getPipName(PipId pip) const override;
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IdString getPipType(PipId pip) const override;
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const std::map<IdString, std::string> &getPipAttrs(PipId pip) const override;
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uint32_t getPipChecksum(PipId pip) const override;
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void bindPip(PipId pip, NetInfo *net, PlaceStrength strength) override;
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void unbindPip(PipId pip) override;
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bool checkPipAvail(PipId pip) const override;
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bool checkPipAvailForNet(PipId pip, const NetInfo *net) const override;
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NetInfo *getBoundPipNet(PipId pip) const override;
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WireId getConflictingPipWire(PipId pip) const override;
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NetInfo *getConflictingPipNet(PipId pip) const override;
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linear_range<PipId> getPips() const override;
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Loc getPipLocation(PipId pip) const override;
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WireId getPipSrcWire(PipId pip) const override;
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WireId getPipDstWire(PipId pip) const override;
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DelayQuad getPipDelay(PipId pip) const override;
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const std::vector<PipId> &getPipsDownhill(WireId wire) const override;
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const std::vector<PipId> &getPipsUphill(WireId wire) const override;
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GroupId getGroupByName(IdStringList name) const override;
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IdStringList getGroupName(GroupId group) const override;
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std::vector<GroupId> getGroups() const override;
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const std::vector<BelId> &getGroupBels(GroupId group) const override;
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const std::vector<WireId> &getGroupWires(GroupId group) const override;
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const std::vector<PipId> &getGroupPips(GroupId group) const override;
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const std::vector<GroupId> &getGroupGroups(GroupId group) const override;
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delay_t estimateDelay(WireId src, WireId dst) const override;
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delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
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delay_t getDelayEpsilon() const override { return delay_epsilon; }
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delay_t getRipupDelayPenalty() const override { return ripup_penalty; }
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float getDelayNS(delay_t v) const override { return v; }
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delay_t getDelayFromNS(float ns) const override { return ns; }
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uint32_t getDelayChecksum(delay_t v) const override { return 0; }
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BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override;
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bool pack() override;
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bool place() override;
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bool route() override;
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std::vector<IdString> getCellTypes() const override
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{
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if (uarch)
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return uarch->getCellTypes();
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pool<IdString> cell_types;
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for (auto bel : bels) {
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cell_types.insert(bel.type);
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}
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return std::vector<IdString>{cell_types.begin(), cell_types.end()};
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}
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std::vector<BelBucketId> getBelBuckets() const override { return getCellTypes(); }
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IdString getBelBucketName(BelBucketId bucket) const override { return bucket; }
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BelBucketId getBelBucketByName(IdString bucket) const override { return bucket; }
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BelBucketId getBelBucketForBel(BelId bel) const override
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{
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return uarch ? uarch->getBelBucketForBel(bel) : getBelType(bel);
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}
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BelBucketId getBelBucketForCellType(IdString cell_type) const override
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{
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return uarch ? uarch->getBelBucketForCellType(cell_type) : cell_type;
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}
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std::vector<BelId> getBelsInBucket(BelBucketId bucket) const override
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{
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std::vector<BelId> bels;
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for (BelId bel : getBels()) {
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if (bucket == getBelBucketForBel(bel)) {
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bels.push_back(bel);
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}
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}
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return bels;
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}
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const std::vector<GraphicElement> &getDecalGraphics(DecalId decal) const override;
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DecalXY getBelDecal(BelId bel) const override;
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DecalXY getWireDecal(WireId wire) const override;
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DecalXY getPipDecal(PipId pip) const override;
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DecalXY getGroupDecal(GroupId group) const override;
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bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const override;
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// Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port
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TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const override;
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// Get the TimingClockingInfo of a port
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TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const override;
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bool isValidBelForCellType(IdString cell_type, BelId bel) const override
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{
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return uarch ? uarch->isValidBelForCellType(cell_type, bel) : cell_type == getBelType(bel);
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}
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bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override;
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static const std::string defaultPlacer;
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static const std::vector<std::string> availablePlacers;
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static const std::string defaultRouter;
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static const std::vector<std::string> availableRouters;
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// ---------------------------------------------------------------
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// Internal usage
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void assignArchInfo() override;
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bool cellsCompatible(const CellInfo **cells, int count) const;
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float delay_epsilon = 0.001;
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float ripup_penalty = 0.015;
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};
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NEXTPNR_NAMESPACE_END
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#endif /* GENERIC_ARCH_H */
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