nextpnr/generic/examples
gatecat 59874188a6 generic: Refactor for faster performance
This won't affect Python-built arches significantly; but will be useful
for the future 'viaduct' functionality where generic routing graphs can
be built on the C++ side; too.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-30 11:54:08 +00:00
..
__init__.py generic/examples: Add FASM writer Python script 2019-04-17 11:00:23 +01:00
.gitignore generic: Add support for post-PnR simulation 2019-11-27 15:17:53 +00:00
bitstream.py return FF_USED, formatting, correct INIT 2019-11-08 17:15:12 +01:00
blinky_tb.v generic: Add support for post-PnR simulation 2019-11-27 15:17:53 +00:00
blinky.v generic: Add support for post-PnR simulation 2019-11-27 15:17:53 +00:00
README.md generic/examples: Add FASM writer Python script 2019-04-17 11:00:23 +01:00
simple_config.py generic/examples: Add FASM writer Python script 2019-04-17 11:00:23 +01:00
simple_timing.py dedicated output for LUT in GENERIC_SLICE 2019-11-08 15:54:27 +01:00
simple.py Add getBelHidden and add some missing "override" statements. 2021-02-11 14:58:02 -08:00
simple.sh dedicated output for LUT in GENERIC_SLICE 2019-11-08 15:54:27 +01:00
simtest.sh generic: Add support for post-PnR simulation 2019-11-27 15:17:53 +00:00
write_fasm.py generic: Refactor for faster performance 2021-12-30 11:54:08 +00:00

Generic Architecture Example

This contains a simple, artificial, example of the nextpnr generic API.

  • simple.py procedurally generates a simple FPGA architecture with IO at the edges, logic slices in all other tiles, and interconnect only between adjacent tiles

  • simple_timing.py annotates cells with timing data (this is a separate script that must be run after packing)

  • write_fasm.py uses the nextpnr Python API to write a FASM file for a design

  • bitstream.py uses write_fasm.py to create a FASM ("FPGA assembly") file for the place-and-routed design

  • Run simple.sh to build an example design on the FPGA above