5a807110de
* ng-ultra: new architecture * Implementation as in D2 deliverable * Support for nxdesignsuite-24.0.0.0-20240429T102300 * Save memory by directly outputing json * Add support for bidirectional IOs * cleanup * Create BFRs properly * Add IOM insertion * Cleanup * Block certain pips depending of DDFR mode * Add LUT bypass to improve routability * Add bypass for CSC mode of GCK * Fix IOM case * Initial memory support * Better RF/XRF handling * fix * RF placement and legalization * Disconnect non available ports for NX_RAM * cleanup * Add RFB/RAM context support for latest release * Remove ports that must not be used * Proper port used only on RFB * Add structure for clock sinks * Use cell type where applicable * Add clock sinks for other cell types * Validation check fixes * Commented too restrictive placement * Added more crossbar wire type * Hande IO termination input * Fail early due to NX tools limitation for now * Validations and fixes for RAM I/Os * Fix for latest version of tools * Use ctx->idf where applicable * warn if RAM ports are not actually used * Fix IOM packing * Fix CY packing * Change how constants are handled on CY * Post placement optimization for CY * Address comments for PR * pack and export GCK, WFG and PLL * Cover more global routing cases * Constraing to location if provided * Place at LOC * Pack and export DSP * wip * wip * notes * wip * wip * Validate DSPs * DSP cascading * Check mandatory parameters for DSP * existing gck * wip * export all the rest for bitstream * CDC packing * add more sinks * place FIFO * map rest of FIFO ports * enable pll by default * cleanup * Initial XLUT support * Fix statistics * Properly duplicate GCKs * RRSTO and WRSTO are not used on XFIFO * Fix for latest version of JSON format * Implement GCK limitations * cleanup * cleanup * Add more signals and use lowskew name * cleanup code a bit * Fix wfb * detect cascaded GCKs * Handle DFR * Route dfr clock properly * Cleanup * Cleanup bitstream code * Review issues addressed * Move helper routines * Expose private members for unit tests * cleanup * remove scale factor * make all location helper arrays static * Addressed review comments * Support post-routing CSC and SCC * Support NX_BFF * Place CSS and SCC only on allowed locations * Support latest Impulse * ng_ultra: Expand bounding box further for left-edge IO Signed-off-by: gatecat <gatecat@ds0.me> * Export all IO parameters in bitstream * Handle new CSV order or parameters and additional validation * Add some more undocumented values for CSV * Support for old and new CSV formats * Initial DDFR support * Display warning message once per file * Address review issues * Fix crash on memory access * Make boundbox fit NG-Ultra internal design * Update attributes after dff rewrite * Implement basic NG-Ultra LUT-DFF unit tests * Always use first seen xbar input Signed-off-by: gatecat <gatecat@ds0.me> * Simplified crossbar pip detection * Change order to prevent issues with some unconnected constants * Pack LUT and multiple DFF in stripe * Place DFF chains * Improve large DFF chains * Rename to pack_dff_chains * Better use XLUTs when possible * pack output DFF together with XLUT * option to disable XLUT optimiziations * Make more optimizations optional * fix to use pre-increment * GCK for lowskew signals * Bugfix for nets that are not part of lowskew network * Fix bitstream export for PLL cell * Remove separate route lowskew * Allow WFG mode 2 * Merge inverter into GCK * Add CSC per TILE when needed * Improve reusage of existing cell for CSC * Take preferred CSC * Cleanup * When in place CSC size not important * Cleanup * Reset and Load restriction * make csc optimisation optional * Proper count for IO resources * Detect when there is no next cell for DSP chain * Do not incorporate loops in XLUT * Check if output exists * Update copyright for delivery * Make building NG-Ultra chip database optional, follow filename convention * Ported drawing code to new API * Update expandBoundingBox for NG-Ultra * Copyright and license update * Add README information * cleanup and constids * Using ctx->idf where applicable * remove if_using_basecluster * refactor extra data usage * refactor to use create_cell_ptr only * optimized getCSC * optimize critical path a bit * clangformat * disable clangformat where applicable --------- Signed-off-by: gatecat <gatecat@ds0.me> Co-authored-by: Lofty <dan.ravensloft@gmail.com> Co-authored-by: gatecat <gatecat@ds0.me>
727 lines
28 KiB
Python
727 lines
28 KiB
Python
# nextpnr -- Next Generation Place and Route
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#
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# Copyright (C) 2024 The Project Beyond Authors.
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#
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# Permission to use, copy, modify, and/or distribute this software for any
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# purpose with or without fee is hereby granted, provided that the above
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# copyright notice and this permission notice appear in all copies.
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#
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# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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#
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import json
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from os import path
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import sys
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import argparse
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import gzip
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# Configuration flags
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USE_LUT_PERMUTATION = True
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sys.path.append(path.join(path.dirname(__file__), "../../.."))
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from himbaechel_dbgen.chip import *
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@dataclass
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class TileExtraData(BBAStruct):
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name: IdString
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lobe: int = 0
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tile_type: int = 0
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def serialise_lists(self, context: str, bba: BBAWriter):
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pass
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def serialise(self, context: str, bba: BBAWriter):
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bba.u32(self.name.index)
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bba.u8(self.lobe)
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bba.u8(self.tile_type)
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bba.u16(0) # dummy
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@dataclass
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class PipExtraData(BBAStruct):
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name: IdString = field(default_factory=IdString)
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data_type: int = 0
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input: int = 0
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output: int = 0
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def serialise_lists(self, context: str, bba: BBAWriter):
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pass
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def serialise(self, context: str, bba: BBAWriter):
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bba.u32(self.name.index)
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bba.u16(self.data_type)
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bba.u8(self.input)
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bba.u8(self.output)
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@dataclass
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class BelExtraData(BBAStruct):
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flags: int = 0
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def serialise_lists(self, context: str, bba: BBAWriter):
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pass
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def serialise(self, context: str, bba: BBAWriter):
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bba.u32(self.flags)
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PLL_Z = 0
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WFG_C_Z = 1
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WFG_R_Z = 11
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IOM_Z = 136
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RAM_Z = 0
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DSP1_Z = 1
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DSP2_Z = 2
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SOCIF_Z = 0
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SERVICE_Z = 1
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LUT_Z = 0
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CY_Z = 32
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XLUT_Z = CY_Z + 4
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RF_Z = XLUT_Z + 8
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XRF_Z = RF_Z + 2
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FIFO_Z = XRF_Z + 1
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XFIFO_Z = FIFO_Z + 2
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CDC_Z = XFIFO_Z + 1
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XCDC_Z = CDC_Z + 2
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PIP_EXTRA_CROSSBAR = 1
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PIP_EXTRA_MUX = 2
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PIP_EXTRA_BYPASS = 3
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PIP_EXTRA_LUT_PERMUTATION = 4
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PIP_EXTRA_INTERCONNECT = 5
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PIP_EXTRA_VIRTUAL = 6
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BEL_EXTRA_FE_CSC = 1
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BEL_EXTRA_FE_SCC = 2
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TILE_EXTRA_FABRIC = 0
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TILE_EXTRA_TUBE = 1
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TILE_EXTRA_SOC = 2
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TILE_EXTRA_RING = 3
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TILE_EXTRA_FENCE = 4
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def bel_z(tile_type, bel_name, bel_type):
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if tile_type.startswith("CKG"):
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if (bel_type=="PLL"):
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return PLL_Z
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else:
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if bel_name.startswith("WFG.WFG_C"):
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return int(bel_name.replace("WFG.WFG_C","")) + WFG_C_Z -1
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else:
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return int(bel_name.replace("WFG.WFG_R","")) + WFG_R_Z -1
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elif tile_type.startswith("HSSL"):
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if bel_type=="PMA":
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return 0
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elif bel_type=="CRX":
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return int(bel_name.split(".")[0][7:]) * 2 - 1
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else:
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return int(bel_name.split(".")[0][7:]) * 2
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elif tile_type.startswith("IOB") and tile_type in ["IOB0","IOB1","IOB6","IOB7"]: #direct
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sp = bel_name.split(".")
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if bel_type=="IOP":
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return int(sp[0][1:]) * 4
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else:
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return (int(sp[0][3:])-1) * 4 + (1 if sp[1][0]=='I' else 2 if sp[1][0]=='O' else 3)
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elif tile_type.startswith("IOB"): # complex
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sp = bel_name.split(".")
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if bel_type=="IOTP":
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return (int(sp[0][1:3]) *2 + (1 if sp[0][3]=='N' else 0)) * 4
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elif bel_type=="IOM":
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return IOM_Z
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else:
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return (int(sp[0][3:])-1) * 4 + (1 if sp[1][0]=='I' else 2 if sp[1][0]=='O' else 3)
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elif tile_type == "CGB":
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if bel_type=="RAM":
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return RAM_Z
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elif bel_name=="S2.DSP1":
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return DSP1_Z
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else:
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return DSP2_Z
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elif tile_type == "SOCBank":
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if bel_type=="SOCIF":
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return SOCIF_Z
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else:
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return SERVICE_Z
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elif tile_type == "TILE":
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sp = bel_name.split(".")
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if bel_type=="BEYOND_FE":
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return (int(sp[1][2:])-1) % 32
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elif bel_type=="CY":
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pos = int(sp[1][2:])-1
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# in S1, S5 and S9 they are ordered other way arround
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return ((pos % 4) if pos < 12 else 3 - (pos % 4)) + CY_Z
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elif bel_type=="XLUT":
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return (int(sp[1][4:])-1) % 8 + XLUT_Z
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elif bel_type=="RF":
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return (int(sp[1][2:])-1) + RF_Z
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elif bel_type=="XRF":
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return (int(sp[1][3:])-1) + XRF_Z
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elif bel_type=="FIFO":
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return (int(sp[1][4:])-1) + FIFO_Z
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elif bel_type=="XFIFO":
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return (int(sp[1][5:])-1) + XFIFO_Z
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elif bel_type=="CDC":
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return (int(sp[1][3:])-1) + CDC_Z
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elif bel_type=="XCDC":
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return (int(sp[1][4:])-1) + XCDC_Z
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else:
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raise Exception(f"Unknown bel type {bel_type}")
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elif tile_type == "TUBE":
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sp = bel_name.split(".")
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return (int(sp[0][1:])-1)*20 + (int(sp[1][1:])-1)
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else:
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raise Exception(f"Unknown type {tile_type}")
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if USE_LUT_PERMUTATION:
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# Note PI1-PI4 are not real inputs but will appear
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# before actual BEL input to enable LUT permutation
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lut_to_beyond_fe = {
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"I1" : "PI1",
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"I2" : "PI2",
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"I3" : "PI3",
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"I4" : "PI4",
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"O" : "LO",
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"J" : "LJ",
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"K" : "LK",
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"D" : "LD",
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"X" : "LX",
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}
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else:
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lut_to_beyond_fe = {
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"I1" : "I1",
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"I2" : "I2",
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"I3" : "I3",
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"I4" : "I4",
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"O" : "LO",
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"J" : "LJ",
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"K" : "LK",
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"D" : "LD",
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"X" : "LX",
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}
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dff_to_beyond_fe = {
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"I" : "DI",
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"O" : "DO",
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"L" : "L",
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"CK" : "CK",
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"R" : "R",
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"J" : "DJ",
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"P" : "DP",
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"C" : "DC",
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"S" : "DS",
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"K" : "DK",
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}
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def is_complex(tile_type):
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return tile_type not in ["IOB0","IOB1","IOB6","IOB7"]
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def map_to_beyond(tile_type,bel_name,bel_type=None):
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if not tile_type in ["TILE"]:
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return (bel_name,bel_type)
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s = bel_name.split(".")
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if tile_type in ["TILE"]:
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# BEYOND_FE
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if not (s[1].startswith("LUT") or s[1].startswith("DFF")):
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return (bel_name,bel_type)
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if len(s)==3:
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# BEL and PORT
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if s[1].startswith("LUT"):
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pin = lut_to_beyond_fe[s[2]]
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else:
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pin = dff_to_beyond_fe[s[2]]
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if pin is None:
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return (None,bel_type)
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return (s[0]+".FE"+s[1][3:]+"."+pin, bel_type if type(bel_type) is int else "BEYOND_FE")
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else:
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# just BEL
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return (s[0]+".FE"+s[1][3:], "BEYOND_FE")
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split_map = ["TILE", "CGB"]
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def split_tilegrid(tilegrid):
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new_tilegrid = dict()
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for k,v in tilegrid.items():
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if v["type"] not in split_map:
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new_tilegrid[k] = dict()
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data = dict(v)
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data["orig"] = data["type"]
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data["x"]=data["x"]*4
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data["y"]=data["y"]*4
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new_tilegrid[k][0] = data
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else:
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new_tilegrid[k] = dict()
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for i in range(4*4):
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data = dict(v)
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data["orig"] = data["type"]
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data["type"] = data["type"]+"_"+str(i)
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data["x"]=data["x"]*4 + i // 4
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data["y"]=data["y"]*4 + i % 4
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new_tilegrid[k][i] = data
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return new_tilegrid
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def determine_subtile(tile,bel):
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if tile=="TILE":
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if bel.startswith("SYSTEM"):
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s = 3
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elif bel.startswith("RE") or bel.startswith("RS") or bel.startswith("RI"):
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s = int(bel.split(".")[0][2:])-1
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elif bel.startswith("S"):
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s = int(bel.split(".")[0][1:])+3
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else:
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return 0
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return s
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elif tile=="CGB":
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if bel.startswith("SYSTEM"):
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s = 6
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elif bel.startswith("RE"):
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s = 8
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elif bel.startswith("RS"):
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s = int(bel.split(".")[0][2:])
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elif bel.startswith("RI"):
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s = 5
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elif bel.startswith("S1"):
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s = 0
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elif bel.startswith("S2.DSP1"):
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s = 7
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else:
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return 15
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return s
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else:
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return 0
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def split_per_bels(bels):
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new_bels = dict()
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for k,v in bels.items():
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if k not in split_map:
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new_bels[k] = dict()
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data = dict(v)
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new_bels[k][0] = data
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else:
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new_bels[k] = dict()
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for i in range(4*4):
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new_bels[k][i] = dict()
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for item,bel in v.items():
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(item, bel) = map_to_beyond(k,item,bel)
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if item is not None:
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num = determine_subtile(k,item)
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new_bels[k][num][item] = bel
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return new_bels
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def lookup_port_type(t):
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if t == "Input": return PinType.INPUT
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elif t == "Output": return PinType.OUTPUT
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elif t == "Bidir": return PinType.INOUT
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else: assert False
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def create_pips(tt, tile_type, muxes, num, args):
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file_path = path.join(args.db, args.device, tile_type + ".txt")
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if not path.isfile(file_path):
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return
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with open(file_path) as f:
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for item in f:
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line = item.strip().split(" ")
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name1,_ = map_to_beyond(tile_type,line[0])
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name2,_ = map_to_beyond(tile_type,line[1])
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if name1 is None or name2 is None:
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continue
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num1 = determine_subtile(tile_type,name1)
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num2 = determine_subtile(tile_type,name2)
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if name2 in muxes:
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name2 = name2 + "." + line[2]
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if num1==num and not tt.has_wire(name1):
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tt.create_wire(name=name1, type=tile_type + "_WIRE")
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if num2==num and not tt.has_wire(name2):
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tt.create_wire(name=name2, type=tile_type + "_WIRE")
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timing_class = line[3]
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# Only create PIP if both ends are in same subtile
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if num1==num and num2==num:
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tt.create_pip(name1,name2,timing_class)
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def create_tile_types(ch: Chip, bels, bel_pins, crossbars, interconnects, muxes, args):
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for tile_type,items in bels.items():
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for num in items.keys():
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if len(items)==1:
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sub_type = tile_type
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else:
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sub_type = f"{tile_type}_{num}"
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tt = ch.create_tile_type(sub_type)
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def lookup_site_wire(canon_name):
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if not tt.has_wire(canon_name):
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tt.create_wire(name=canon_name, type="BEL_PIN_WIRE")
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return canon_name
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# Create BELs inside tile
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for name,bel in bels[tile_type][num].items():
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nb = tt.create_bel(name, bel, z=bel_z(tile_type,name,bel))
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# Create wires for each BEL port
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for index in bel_pins[bel].keys():
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pin = bel_pins[bel][index]
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tt.add_bel_pin(nb, pin["name"], lookup_site_wire(f"{name}."+pin["name"]), lookup_port_type(pin["direction"]))
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if (tile_type.startswith("TILE") and bel=="BEYOND_FE"):
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flag = 0
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fe_nxd = int(name[name.index(".")+3:])
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if (((fe_nxd-1) & 127) < 64):
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if ((fe_nxd-1)&31) < 16:
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if (fe_nxd & 1)==1:
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flag |= BEL_EXTRA_FE_SCC
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else:
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if (fe_nxd & 1)==0:
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flag |= BEL_EXTRA_FE_SCC
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if fe_nxd in (65, 80, 81, 96, 225,240,241,256, 321,336,337,352):
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flag |= BEL_EXTRA_FE_CSC
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nb.extra_data = BelExtraData(flag)
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# LUT drawers, LO already connected to LJ
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vi = tt.create_pip(f"{name}.LJ",f"{name}.LK","Virtual")
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vi.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_VIRTUAL,0,0)
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vi = tt.create_pip(f"{name}.LJ",f"{name}.LD","Virtual")
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vi.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_VIRTUAL,0,0)
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vi = tt.create_pip(f"{name}.LJ",f"{name}.LX","Virtual")
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vi.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_VIRTUAL,0,0)
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# DFF drawers, DO already connected to DJ
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vi = tt.create_pip(f"{name}.DJ",f"{name}.DP","Virtual")
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vi.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_VIRTUAL,0,0)
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vi = tt.create_pip(f"{name}.DJ",f"{name}.DC","Virtual")
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vi.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_VIRTUAL,0,0)
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vi = tt.create_pip(f"{name}.DJ",f"{name}.DS","Virtual")
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vi.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_VIRTUAL,0,0)
|
|
vi = tt.create_pip(f"{name}.DJ",f"{name}.DK","Virtual")
|
|
vi.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_VIRTUAL,0,0)
|
|
# DFF bypass
|
|
by = tt.create_pip(f"{name}.DI",f"{name}.DO","BYPASS")
|
|
by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0)
|
|
# LUT bypass
|
|
by = tt.create_pip(f"{name}.I1",f"{name}.LO","BYPASS")
|
|
by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,1,0)
|
|
elif (tile_type.startswith("TILE") and bel=="XLUT"):
|
|
for out in ["G1","G2","G3","G4"]:
|
|
vi = tt.create_pip(f"{name}.J",f"{name}.{out}","Virtual")
|
|
vi.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_VIRTUAL,0,0)
|
|
elif (tile_type.startswith("TILE") and bel=="CY"):
|
|
# matrix of each input to each output combination
|
|
# crossbar but use mux placeholder for convenience
|
|
for inp in ["I1","I2","I3","I4"]:
|
|
for out in ["O1","O2","O3","O4"]:
|
|
pd = tt.create_pip(f"{name}."+inp,f"{name}."+out,"MATRIX_PIP")
|
|
pd.extra_data = PipExtraData(ch.strs.id(f"{name}."+inp),PIP_EXTRA_MUX,int(inp[1:])-1,int(out[1:])-1)
|
|
|
|
elif (tile_type.startswith("CKG") and bel=="WFG"):
|
|
by = tt.create_pip(f"{name}.ZI",f"{name}.ZO","BYPASS")
|
|
by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0)
|
|
elif (tile_type.startswith("TUBE") and bel=="GCK"):
|
|
# 20 clock signals comming to 20 GCK, SI1 is bypass
|
|
by = tt.create_pip(f"{name}.SI1",f"{name}.SO","BYPASS")
|
|
by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0)
|
|
# there are CMD signals that can be bypassed as well
|
|
by = tt.create_pip(f"{name}.CMD",f"{name}.SO","BYPASS")
|
|
by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,1,0)
|
|
|
|
|
|
# Add LUT permutation
|
|
if USE_LUT_PERMUTATION and tile_type=="TILE":
|
|
for name,bel in bels[tile_type][num].items():
|
|
if bel=="BEYOND_FE":
|
|
for inp in ["PI1","PI2","PI3","PI4"]:
|
|
tt.create_wire(name=f"{name}."+inp, type="LUT_PERMUTATION_WIRE")
|
|
for out in ["I1","I2","I3","I4"]:
|
|
pd = tt.create_pip(f"{name}."+inp,f"{name}."+out,"LUT_PERMUTATION")
|
|
pd.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_LUT_PERMUTATION,int(inp[2:])-1,int(out[1:])-1)
|
|
|
|
# Create crossbars as multiple PIPs
|
|
for name,xb in crossbars[tile_type][num].items():
|
|
inputs = list()
|
|
outputs = list()
|
|
for index in bel_pins[xb].keys():
|
|
pin = bel_pins[xb][index]
|
|
tt.create_wire(name=f"{name}."+pin["name"], type="CROSSBAR_"+xb+"_INPUT_WIRE" if pin["direction"] == "Input" else "CROSSBAR_"+xb+"_OUTPUT_WIRE")
|
|
for index in bel_pins[xb].keys():
|
|
pin = bel_pins[xb][index]
|
|
if pin["direction"] == "Input":
|
|
inputs.append(pin["name"])
|
|
else:
|
|
outputs.append(pin["name"])
|
|
for inp in inputs:
|
|
for out in outputs:
|
|
pd = tt.create_pip(f"{name}."+inp,f"{name}."+out,"CROSSBAR_"+xb)
|
|
pd.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_CROSSBAR,int(inp[1:])-1,int(out[1:])-1)
|
|
|
|
# Interconnects are just PIPs with one I and one O
|
|
for name,xb in interconnects[tile_type][num].items():
|
|
for index in bel_pins[xb].keys():
|
|
pin = bel_pins[xb][index]
|
|
tt.create_wire(name=f"{name}."+pin["name"], type="INTERCONNECT_INPUT" if pin["direction"] == "Input" else "INTERCONNECT_OUTPUT")
|
|
inp = f"{name}."+bel_pins[xb]["I"]["name"]
|
|
out = f"{name}."+bel_pins[xb]["O"]["name"]
|
|
pd = tt.create_pip(inp,out,"INTERCONNECT")
|
|
pd.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_INTERCONNECT,0,0)
|
|
|
|
# Create MUXes as many to one connections
|
|
if tile_type in muxes:
|
|
for (name, n) in muxes[tile_type][num].items():
|
|
for i in range(0,n+1):
|
|
new_name = name + "." + str(i)
|
|
if not tt.has_wire(new_name):
|
|
tt.create_wire(name=new_name, type="MUX_WIRE")
|
|
pd = tt.create_pip(new_name,name,"MUX_PIP")
|
|
pd.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_MUX,i,0)
|
|
|
|
m = muxes[tile_type] if tile_type in muxes else dict()
|
|
mux = muxes[tile_type][num] if num in m else dict()
|
|
create_pips(tt, tile_type, mux, num, args)
|
|
|
|
def create_null(ch: Chip):
|
|
tt = ch.create_tile_type("NULL")
|
|
|
|
def set_timings(ch, pip_timings, bel_timings):
|
|
speed = "DEFAULT"
|
|
tmg = ch.set_speed_grades([speed])
|
|
for k,v in pip_timings.items():
|
|
tmg.set_pip_class(grade=speed, name=k, delay=TimingValue(v[0]))
|
|
tmg.set_node_class(grade=speed, name=k, delay=TimingValue(v[0]))
|
|
tmg.set_pip_class(grade=speed, name="INTERCONNECT", delay=TimingValue(0))
|
|
tmg.set_pip_class(grade=speed, name="MUX_PIP", delay=TimingValue(0))
|
|
tmg.set_pip_class(grade=speed, name="MATRIX_PIP", delay=TimingValue(0))
|
|
tmg.set_pip_class(grade=speed, name="LUT_PERMUTATION", delay=TimingValue(0))
|
|
tmg.set_pip_class(grade=speed, name="BYPASS", delay=TimingValue(142))
|
|
for k,g in bel_timings.items():
|
|
primitive = ch.timing.add_cell_variant(speed, k)
|
|
for t,v in g.items():
|
|
if t=="IOPath":
|
|
for from_port,values in v.items():
|
|
for to_port,data in values.items():
|
|
primitive.add_comb_arc(from_port, to_port, TimingValue(data[0], data[1]))
|
|
elif t=="SetupHold":
|
|
for from_port,values in v.items():
|
|
for to_port,data in values.items():
|
|
primitive.add_setup_hold(from_port, to_port, ClockEdge.RISING, TimingValue(data[0]), TimingValue(data[1]))
|
|
elif t=="ClockOut":
|
|
for from_port,values in v.items():
|
|
for to_port,data in values.items():
|
|
primitive.add_clock_out(from_port, to_port, ClockEdge.RISING, TimingValue(data[0],data[1]))
|
|
|
|
def get_pos(tilegrid,name,bel):
|
|
tile = tilegrid[name][0]["orig"]
|
|
num = determine_subtile(tile,bel)
|
|
item = tilegrid[name][num]
|
|
x = item["x"]
|
|
y = item["y"]
|
|
return (tile,num,x,y)
|
|
|
|
|
|
global_connections = dict()
|
|
def load_globals(args):
|
|
print("Load global connections...")
|
|
with gzip.open(path.join(args.db, args.device, "GLOBAL.txt.gz"),"rt") as f:
|
|
for item in f:
|
|
line = item.strip().split(" ")
|
|
tile_name = line[0].split(":")[0]
|
|
if tile_name not in global_connections:
|
|
global_connections[tile_name] = dict()
|
|
if line[0] not in global_connections[tile_name]:
|
|
global_connections[tile_name][line[0]] = list()
|
|
global_connections[tile_name][line[0]].append(line)
|
|
|
|
def create_nodes(ch, tile_name, tilegrid, muxes, pip_timings):
|
|
if tile_name not in global_connections:
|
|
return
|
|
connections = global_connections[tile_name]
|
|
for key,val in connections.items():
|
|
name1 = key.split(":")
|
|
t1,_,x1,y1 = get_pos(tilegrid,name1[0],name1[1])
|
|
name1[1],_ = map_to_beyond(t1,name1[1])
|
|
if name1[1] is None:
|
|
continue
|
|
node = [NodeWire(x1, y1, name1[1])]
|
|
timing = None
|
|
timing_val = -1
|
|
for v in val:
|
|
name2 = v[1].split(":")
|
|
name2[1],_ = map_to_beyond(tilegrid[name2[0]][0]["orig"],name2[1])
|
|
t2,num,x2,y2 = get_pos(tilegrid,name2[0],name2[1])
|
|
if name2[1] is None:
|
|
continue
|
|
if pip_timings[v[3]][0] > timing_val:
|
|
timing_val = pip_timings[v[3]][0]
|
|
timing = v[3]
|
|
if t2 in muxes and num in muxes[t2] and name2[1] in muxes[t2][num]:
|
|
node.append(NodeWire(x2, y2, name2[1]+"."+v[2]))
|
|
else:
|
|
node.append(NodeWire(x2, y2, name2[1]))
|
|
|
|
ch.add_node(node,timing_class=timing)
|
|
|
|
|
|
subtile_connections = dict()
|
|
def create_nodes_subtiles(ch, tilegrid, name, tile_type, muxes, pip_timings, args):
|
|
if tile_type not in subtile_connections:
|
|
subtile_connections[tile_type] = dict()
|
|
|
|
file_path = path.join(args.db, args.device, tile_type + ".txt")
|
|
if not path.isfile(file_path):
|
|
return
|
|
with open(file_path) as f:
|
|
for item in f:
|
|
line = item.strip().split(" ")
|
|
name1 = line[0]
|
|
name2 = line[1]
|
|
name1,_ = map_to_beyond(tile_type,line[0])
|
|
name2,_ = map_to_beyond(tile_type,line[1])
|
|
if name1 is None or name2 is None:
|
|
continue
|
|
num1 = determine_subtile(tile_type,name1)
|
|
num2 = determine_subtile(tile_type,name2)
|
|
# Only create WIRE if ends are NOT in same subtile
|
|
if num1!=num2:
|
|
if name1 not in subtile_connections[tile_type] :
|
|
subtile_connections[tile_type][name1] = list()
|
|
subtile_connections[tile_type][name1].append([name1, name2, line[2], line[3]])
|
|
|
|
for name1,val in subtile_connections[tile_type].items():
|
|
_,_,x1,y1 = get_pos(tilegrid,name,name1)
|
|
node = [NodeWire(x1, y1, name1)]
|
|
timing_val = -1
|
|
timing = None
|
|
for v in val:
|
|
name2 = v[1]
|
|
t2,num,x2,y2 = get_pos(tilegrid,name,name2)
|
|
if pip_timings[v[3]][0] > timing_val:
|
|
timing_val = pip_timings[v[3]][0]
|
|
timing = v[3]
|
|
if t2 in muxes and num in muxes[t2] and name2 in muxes[t2][num]:
|
|
node.append(NodeWire(x2, y2, name2+"."+v[2]))
|
|
else:
|
|
node.append(NodeWire(x2, y2, name2))
|
|
|
|
ch.add_node(node,timing_class=timing)
|
|
|
|
def import_package(ch, package, bels, tilegrid):
|
|
pkg = ch.create_package(package)
|
|
for name, data in tilegrid.items():
|
|
for key, item in data.items():
|
|
ty = item["orig"]
|
|
x = item["x"]
|
|
y = item["y"]
|
|
if ty.startswith("IOB"):
|
|
for bel,ty in bels[ty][key].items():
|
|
# Support for native primitives
|
|
if ty =="IOTP":
|
|
pin = name+"_"+bel[:4]
|
|
elif ty =="IOP":
|
|
pin = name+"_"+bel[:3]
|
|
else:
|
|
continue
|
|
pkg.create_pad(pin, f"X{x}Y{y}", bel, "", int(name[3:]))
|
|
|
|
def main():
|
|
xlbase = path.join(path.dirname(path.realpath(__file__)), "..")
|
|
|
|
parser = argparse.ArgumentParser()
|
|
parser.add_argument("--db", help="Project Beyond device database path (e.g. ../prjbeyond/database)", type=str, required=True)
|
|
parser.add_argument("--device", help="name of device to export", type=str, required=True)
|
|
parser.add_argument("--constids", help="name of nextpnr constids file to read", type=str, default=path.join(xlbase, "constids.inc"))
|
|
parser.add_argument("--bba", help="bba file to write", type=str, required=True)
|
|
args = parser.parse_args()
|
|
|
|
with open(path.join(args.db, "devices.json")) as f:
|
|
devices = json.load(f)
|
|
|
|
width = (devices["families"][args.device]["max_col"] + 1) * 4
|
|
height = (devices["families"][args.device]["max_row"] + 1) * 4
|
|
packages = devices["families"][args.device]["packages"]
|
|
|
|
ch = Chip("ng-ultra",args.device, width, height)
|
|
ch.strs.read_constids(path.join(path.dirname(__file__), "..", "constids.inc"))
|
|
|
|
# Data that is depending of location
|
|
with open(path.join(args.db, args.device, "tilegrid.json")) as f:
|
|
tilegrid = split_tilegrid(json.load(f))
|
|
|
|
with open(path.join(args.db, args.device, "bels.json")) as f:
|
|
bels = split_per_bels(json.load(f))
|
|
|
|
with open(path.join(args.db, args.device, "crossbars.json")) as f:
|
|
crossbars = split_per_bels(json.load(f))
|
|
|
|
with open(path.join(args.db, args.device, "interconnects.json")) as f:
|
|
interconnects = split_per_bels(json.load(f))
|
|
|
|
with open(path.join(args.db, args.device, "muxes.json")) as f:
|
|
muxes = split_per_bels(json.load(f))
|
|
|
|
# Data that is not related to position
|
|
with open(path.join(args.db, args.device, "bel_pins.json")) as f:
|
|
bel_pins = json.load(f)
|
|
bel_pins["IOP"]["IO"] = { "direction": "Bidir", "name": "IO" }
|
|
bel_pins["IOTP"]["IO"] = { "direction": "Bidir", "name": "IO" }
|
|
|
|
with open(path.join(args.db, args.device, "pip_timings.json")) as f:
|
|
pip_timings = json.load(f)
|
|
|
|
with open(path.join(args.db, args.device, "bel_timings.json")) as f:
|
|
bel_timings = json.load(f)
|
|
|
|
create_tile_types(ch, bels, bel_pins, crossbars, interconnects, muxes, args)
|
|
create_null(ch)
|
|
set_timings(ch, pip_timings, bel_timings)
|
|
|
|
for x in range(width):
|
|
for y in range(height):
|
|
ch.set_tile_type(x,y,"NULL")
|
|
|
|
load_globals(args)
|
|
for name, data in tilegrid.items():
|
|
for item in data.values():
|
|
ti = ch.set_tile_type(item["x"],item["y"],item["type"])
|
|
lobe = 0
|
|
if item["orig"] in ["TILE","CGB"]:
|
|
tmp = name.replace("TILE[","").replace("CGB[","").replace("]","")
|
|
x,y = tmp.split("x")
|
|
lobe = ((int(y)-1) // 12)*2 + (1 if int(x)>46 else 0) + 1
|
|
elif item["orig"].startswith("IOB") or item["orig"].startswith("HSSL"):
|
|
match item["orig"]:
|
|
case "IOB0" | "IOB1":
|
|
lobe = 5
|
|
case "IOB6" | "IOB7":
|
|
lobe = 6
|
|
case "IOB8" | "IOB9" | "IOB10":
|
|
lobe = 2
|
|
case "IOB11" | "IOB12" | "IOB13":
|
|
lobe = 1
|
|
case "IOB2" | "IOB3" | "HSSL0" | "HSSL1" | "HSSL2" | "HSSL3":
|
|
lobe = 7
|
|
case "IOB4" | "IOB5" | "HSSL4" | "HSSL5" | "HSSL6" | "HSSL7":
|
|
lobe = 8
|
|
tile_type = 0
|
|
if item["orig"] in ["TILE","CGB","MESH"]:
|
|
tile_type = TILE_EXTRA_FABRIC
|
|
elif item["orig"] in ["TUBE"]:
|
|
tile_type = TILE_EXTRA_TUBE
|
|
elif item["orig"] in ["SOCBank"]:
|
|
tile_type = TILE_EXTRA_SOC
|
|
elif item["orig"].startswith("IOB") or item["orig"].startswith("HSSL") or item["orig"].startswith("CKG"):
|
|
tile_type = TILE_EXTRA_RING
|
|
elif item["orig"].startswith("FENCE"):
|
|
tile_type = TILE_EXTRA_FENCE
|
|
|
|
ti.extra_data = TileExtraData(ch.strs.id(name),lobe, tile_type)
|
|
|
|
for name, data in tilegrid.items():
|
|
print(f"Generate nodes for {name}...")
|
|
create_nodes_subtiles(ch, tilegrid, name, data[0]["orig"], muxes, pip_timings, args)
|
|
create_nodes(ch, name, tilegrid, muxes, pip_timings)
|
|
|
|
for package in packages:
|
|
import_package(ch, package, bels, tilegrid)
|
|
|
|
ch.write_bba(args.bba)
|
|
|
|
if __name__ == '__main__':
|
|
main()
|