24 lines
425 B
Verilog
24 lines
425 B
Verilog
module counter_tb;
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reg clk;
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always #5 clk = (clk === 1'b0);
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wire outa, outb, outc, outd;
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chip uut (
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.clk(clk),
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.cen(1'b1),
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.rst(1'b0),
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.outa(outa),
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.outb(outb),
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.outc(outc),
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.outd(outd)
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);
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initial begin
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$dumpfile("counter_tb.vcd");
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$dumpvars(0, counter_tb);
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repeat (100000) @(posedge clk);
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$finish;
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end
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endmodule
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