55 lines
614 B
Verilog
55 lines
614 B
Verilog
module top(input clk, cen, rst, ina, inb, output outa, outb, outc, outd);
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wire temp0, temp1;
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(* BEL="1_1_lc0" *)
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SB_LUT4 #(
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.LUT_INIT(2'b01)
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) lut0 (
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.I3(),
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.I2(),
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.I1(),
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.I0(ina),
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.O(temp0)
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);
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(* BEL="1_3_lc0" *)
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SB_LUT4 #(
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.LUT_INIT(2'b01)
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) lut1 (
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.I3(),
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.I2(),
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.I1(),
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.I0(inb),
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.O(temp1)
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);
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(* BEL="1_1_lc0" *)
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SB_DFF ff0 (
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.C(clk),
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.D(temp1),
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.Q(outa)
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);
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(* BEL="1_1_lc7" *)
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SB_DFF ff1 (
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.C(clk),
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.D(inb),
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.Q(outb)
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);
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(* BEL="1_6_lc7" *)
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SB_DFF ff2 (
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.C(clk),
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.D(temp1),
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.Q(outc)
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);
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assign outd = 1'b0;
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endmodule
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