128 lines
3.2 KiB
Verilog
128 lines
3.2 KiB
Verilog
/*
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* ECP5 PicoRV32 demo
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*
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* Copyright (C) 2017 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2018 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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`ifdef PICORV32_V
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`error "attosoc.v must be read before picorv32.v!"
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`endif
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`define PICORV32_REGS picosoc_regs
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module attosoc (
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input clk,
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output reg [7:0] led
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);
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reg [5:0] reset_cnt = 0;
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wire resetn = &reset_cnt;
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always @(posedge clk) begin
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reset_cnt <= reset_cnt + !resetn;
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end
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parameter integer MEM_WORDS = 256;
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parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
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parameter [31:0] PROGADDR_RESET = 32'h 0000_0000; // ROM at 0x0
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parameter integer ROM_BYTES = 256;
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reg [7:0] rom [0:ROM_BYTES-1];
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wire [31:0] rom_rdata = {rom[mem_addr+3], rom[mem_addr+2], rom[mem_addr+1], rom[mem_addr+0]};
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initial $readmemh("firmware.hex", rom);
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wire mem_valid;
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wire mem_instr;
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wire mem_ready;
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wire [31:0] mem_addr;
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wire [31:0] mem_wdata;
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wire [3:0] mem_wstrb;
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wire [31:0] mem_rdata;
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wire rom_ready = mem_valid && mem_addr[31:24] == 8'h00;
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wire iomem_valid;
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wire iomem_ready;
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wire [31:0] iomem_addr;
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wire [31:0] iomem_wdata;
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wire [3:0] iomem_wstrb;
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wire [31:0] iomem_rdata;
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assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
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assign iomem_ready = 1'b1;
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assign iomem_wstrb = mem_wstrb;
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assign iomem_addr = mem_addr;
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assign iomem_wdata = mem_wdata;
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wire [31:0] spimemio_cfgreg_do;
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always @(posedge clk)
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if (iomem_valid && iomem_wstrb[0])
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led <= iomem_wdata[7:0];
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assign mem_ready = (iomem_valid && iomem_ready) || rom_ready;
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assign mem_rdata = rom_rdata;
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picorv32 #(
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.STACKADDR(STACKADDR),
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.PROGADDR_RESET(PROGADDR_RESET),
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.PROGADDR_IRQ(32'h 0000_0000),
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.BARREL_SHIFTER(0),
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.COMPRESSED_ISA(0),
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.ENABLE_MUL(0),
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.ENABLE_DIV(0),
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.ENABLE_IRQ(0),
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.ENABLE_IRQ_QREGS(0)
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) cpu (
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.clk (clk ),
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.resetn (resetn ),
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.mem_valid (mem_valid ),
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.mem_instr (mem_instr ),
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.mem_ready (mem_ready ),
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.mem_addr (mem_addr ),
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.mem_wdata (mem_wdata ),
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.mem_wstrb (mem_wstrb ),
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.mem_rdata (mem_rdata )
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);
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endmodule
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// Implementation note:
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// Replace the following two modules with wrappers for your SRAM cells.
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module picosoc_regs (
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input clk, wen,
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input [5:0] waddr,
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input [5:0] raddr1,
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input [5:0] raddr2,
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input [31:0] wdata,
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output [31:0] rdata1,
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output [31:0] rdata2
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);
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reg [31:0] regs [0:31];
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always @(posedge clk)
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if (wen) regs[waddr[4:0]] <= wdata;
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assign rdata1 = regs[raddr1[4:0]];
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assign rdata2 = regs[raddr2[4:0]];
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endmodule
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