33 lines
519 B
Verilog
33 lines
519 B
Verilog
module testbench();
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integer out;
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reg clk;
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always #5 clk = (clk === 1'b0);
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initial begin
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out = $fopen("output.txt","w");
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$dumpfile("testbench.vcd");
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$dumpvars(0, testbench);
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repeat (100) begin
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repeat (256) @(posedge clk);
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$display("+256 cycles");
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end
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$fclose(out);
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#100;
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$finish;
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end
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wire [7:0] led;
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always @(led) begin
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#1 $display("%b", led);
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$fwrite(out, "%b\n", led);
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end
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attosoc uut (
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.clk (clk ),
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.led (led )
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);
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endmodule
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