20 lines
329 B
Verilog
20 lines
329 B
Verilog
// Modified from:
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// https://github.com/tinyfpga/TinyFPGA-A-Series/tree/master/template_a2
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module top (
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(* LOC="13" *)
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output pin1,
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(* LOC="21" *)
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input clk
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);
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reg [23:0] led_timer;
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always @(posedge clk) begin
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led_timer <= led_timer + 1;
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end
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// left side of board
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assign pin1 = led_timer[23];
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endmodule
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