696 lines
26 KiB
Python
696 lines
26 KiB
Python
#!/usr/bin/env python3
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import argparse
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import json
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import sys
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from os import path
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tiletype_names = dict()
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gfx_wire_ids = dict()
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gfx_wire_names = list()
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parser = argparse.ArgumentParser(description="import MachXO2 routing and bels from Project Trellis")
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parser.add_argument("device", type=str, help="target device")
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parser.add_argument("-p", "--constids", type=str, help="path to constids.inc")
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parser.add_argument("-g", "--gfxh", type=str, help="path to gfx.h")
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parser.add_argument("-L", "--libdir", type=str, action="append", help="extra Python library path")
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args = parser.parse_args()
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sys.path += args.libdir
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import pytrellis
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import database
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import pip_classes
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import timing_dbs
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with open(args.gfxh) as f:
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state = 0
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for line in f:
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if state == 0 and line.startswith("enum GfxTileWireId"):
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state = 1
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elif state == 1 and line.startswith("};"):
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state = 0
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elif state == 1 and (line.startswith("{") or line.strip() == ""):
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pass
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elif state == 1:
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idx = len(gfx_wire_ids)
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name = line.strip().rstrip(",")
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gfx_wire_ids[name] = idx
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gfx_wire_names.append(name)
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def wire_type(name):
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return "WIRE_TYPE_NONE"
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# Get the index for a tiletype
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def get_tiletype_index(name):
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if name in tiletype_names:
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return tiletype_names[name]
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idx = len(tiletype_names)
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tiletype_names[name] = idx
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return idx
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def package_shortname(long_name, family):
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if long_name.startswith("CABGA"):
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if (family == "MachXO"):
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return "B" + long_name[5:]
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else:
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return "BG" + long_name[5:]
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elif long_name.startswith("CSBGA"):
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if (family == "MachXO"):
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return "M" + long_name[5:]
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else:
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return "MG" + long_name[5:]
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elif long_name.startswith("CSFBGA"):
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return "MG" + long_name[6:]
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elif long_name.startswith("UCBGA"):
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return "UMG" + long_name[5:]
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elif long_name.startswith("FPBGA"):
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return "FG" + long_name[5:]
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elif long_name.startswith("FTBGA"):
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if (family == "MachXO"):
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return "FT" + long_name[5:]
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else:
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return "FTG" + long_name[5:]
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elif long_name.startswith("WLCSP"):
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if (family == "MachXO3D"):
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return "UTG" + long_name[5:]
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else:
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return "UWG" + long_name[5:]
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elif long_name.startswith("TQFP"):
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if (family == "MachXO"):
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return "T" + long_name[4:]
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else:
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return "TG" + long_name[4:]
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elif long_name.startswith("QFN"):
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if (family == "MachXO3D"):
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return "SG" + long_name[3:]
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else:
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if long_name[3]=="8":
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return "QN" + long_name[3:]
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else:
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return "SG" + long_name[3:]
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else:
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print("unknown package name " + long_name)
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sys.exit(-1)
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constids = dict()
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class BinaryBlobAssembler:
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def l(self, name, ltype = None, export = False):
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if ltype is None:
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print("label %s" % (name,))
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else:
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print("label %s %s" % (name, ltype))
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def r(self, name, comment):
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if comment is None:
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print("ref %s" % (name,))
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else:
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print("ref %s %s" % (name, comment))
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def r_slice(self, name, length, comment):
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if comment is None:
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print("ref %s" % (name,))
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else:
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print("ref %s %s" % (name, comment))
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print ("u32 %d" % (length, ))
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def s(self, s, comment):
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assert "|" not in s
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print("str |%s| %s" % (s, comment))
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def u8(self, v, comment):
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assert -128 <= int(v) <= 127
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if comment is None:
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print("u8 %d" % (v,))
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else:
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print("u8 %d %s" % (v, comment))
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def u16(self, v, comment):
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# is actually used as signed 16 bit
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assert -32768 <= int(v) <= 32767
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if comment is None:
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print("u16 %d" % (v,))
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else:
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print("u16 %d %s" % (v, comment))
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def u32(self, v, comment):
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if comment is None:
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print("u32 %d" % (v,))
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else:
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print("u32 %d %s" % (v, comment))
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def pre(self, s):
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print("pre %s" % s)
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def post(self, s):
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print("post %s" % s)
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def push(self, name):
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print("push %s" % name)
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def pop(self):
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print("pop")
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def get_bel_index(rg, loc, name):
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tile = rg.tiles[loc]
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idx = 0
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for bel in tile.bels:
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if rg.to_str(bel.name) == name:
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return idx
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idx += 1
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# FIXME: I/O pins can be missing in various rows. Is there a nice way to
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# assert on each device size?
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return None
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packages = {}
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pindata = []
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variants = {}
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def process_devices_db(family, device):
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devicefile = path.join(database.get_db_root(), "devices.json")
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with open(devicefile, 'r') as f:
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devicedb = json.load(f)
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for varname, vardata in sorted(devicedb["families"][family]["devices"][device]["variants"].items()):
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variants[varname] = vardata
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def process_pio_db(rg, device):
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piofile = path.join(database.get_db_root(), dev_family[device], dev_names[device], "iodb.json")
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with open(piofile, 'r') as f:
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piodb = json.load(f)
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for pkgname, pkgdata in sorted(piodb["packages"].items()):
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pins = []
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for name, pinloc in sorted(pkgdata.items()):
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x = pinloc["col"]
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y = pinloc["row"]
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loc = pytrellis.Location(x, y)
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pio = "PIO" + pinloc["pio"]
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bel_idx = get_bel_index(rg, loc, pio)
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if bel_idx is not None:
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pins.append((name, loc, bel_idx))
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packages[pkgname] = pins
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for metaitem in piodb["pio_metadata"]:
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x = metaitem["col"]
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y = metaitem["row"]
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loc = pytrellis.Location(x, y)
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pio = "PIO" + metaitem["pio"]
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bank = metaitem["bank"]
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if "function" in metaitem:
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pinfunc = metaitem["function"]
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else:
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pinfunc = None
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dqs = -1
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if "dqs" in metaitem:
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pass
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# tdqs = metaitem["dqs"]
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# if tdqs[0] == "L":
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# dqs = 0
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# elif tdqs[0] == "R":
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# dqs = 2048
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# suffix_size = 0
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# while tdqs[-(suffix_size+1)].isdigit():
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# suffix_size += 1
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# dqs |= int(tdqs[-suffix_size:])
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bel_idx = get_bel_index(rg, loc, pio)
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if bel_idx is not None:
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pindata.append((loc, bel_idx, bank, pinfunc, dqs))
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speed_grade_names = {
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"MachXO2": ["1", "2", "3", "4", "5", "6"],
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"MachXO3": ["5", "6"],
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"MachXO3D": ["2", "3", "5", "6"]
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}
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speed_grade_cells = {}
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speed_grade_pips = {}
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pip_class_to_idx = {"default": 0, "zero": 1}
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timing_port_xform = {
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"RAD0": "A0",
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"RAD1": "B0",
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"RAD2": "C0",
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"RAD3": "D0",
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}
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delay_db = {}
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# Convert from Lattice-style grouped SLICE to new nextpnr split style SLICE
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def postprocess_timing_data(cells):
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def delay_diff(x, y):
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return (x[0] - y[0], x[1] - y[1])
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split_cells = {}
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comb_delays = {}
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comb_delays[("A", "F")] = delay_db["SLICE"][("A0", "F0")]
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comb_delays[("B", "F")] = delay_db["SLICE"][("B0", "F0")]
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comb_delays[("C", "F")] = delay_db["SLICE"][("C0", "F0")]
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comb_delays[("D", "F")] = delay_db["SLICE"][("D0", "F0")]
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comb_delays[("A", "OFX")] = delay_db["SLICE"][("A0", "OFX0")]
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comb_delays[("B", "OFX")] = delay_db["SLICE"][("B0", "OFX0")]
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comb_delays[("C", "OFX")] = delay_db["SLICE"][("C0", "OFX0")]
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comb_delays[("D", "OFX")] = delay_db["SLICE"][("D0", "OFX0")]
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comb_delays[("M", "OFX")] = delay_db["SLICE"][("M0", "OFX0")] # worst case
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comb_delays[("F1", "OFX")] = delay_diff(delay_db["SLICE"][("A1", "OFX0")],
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delay_db["SLICE"][("A1", "F1")])
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comb_delays[("FXA", "OFX")] = delay_db["SLICE"][("FXA", "OFX1")]
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comb_delays[("FXB", "OFX")] = delay_db["SLICE"][("FXB", "OFX1")]
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split_cells["TRELLIS_COMB"] = comb_delays
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carry0_delays = {}
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carry0_delays[("A", "F")] = delay_db["SLICE"][("A0", "F0")]
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carry0_delays[("B", "F")] = delay_db["SLICE"][("B0", "F0")]
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carry0_delays[("C", "F")] = delay_db["SLICE"][("C0", "F0")]
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carry0_delays[("D", "F")] = delay_db["SLICE"][("D0", "F0")]
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carry0_delays[("A", "FCO")] = delay_db["SLICE"][("A0", "FCO")]
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carry0_delays[("B", "FCO")] = delay_db["SLICE"][("B0", "FCO")]
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carry0_delays[("C", "FCO")] = delay_db["SLICE"][("C0", "FCO")]
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carry0_delays[("D", "FCO")] = delay_db["SLICE"][("D0", "FCO")]
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carry0_delays[("FCI", "F")] = delay_db["SLICE"][("FCI", "F0")]
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carry0_delays[("FCI", "FCO")] = delay_db["SLICE"][("FCI", "FCO")]
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split_cells["TRELLIS_COMB_CARRY0"] = carry0_delays
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carry1_delays = {}
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carry1_delays[("A", "F")] = delay_db["SLICE"][("A1", "F1")]
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carry1_delays[("B", "F")] = delay_db["SLICE"][("B1", "F1")]
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carry1_delays[("C", "F")] = delay_db["SLICE"][("C1", "F1")]
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carry1_delays[("D", "F")] = delay_db["SLICE"][("D1", "F1")]
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carry1_delays[("A", "FCO")] = delay_db["SLICE"][("A1", "FCO")]
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carry1_delays[("B", "FCO")] = delay_db["SLICE"][("B1", "FCO")]
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carry1_delays[("C", "FCO")] = delay_db["SLICE"][("C1", "FCO")]
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carry1_delays[("D", "FCO")] = delay_db["SLICE"][("D1", "FCO")]
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carry1_delays[("FCI", "F")] = delay_diff(delay_db["SLICE"][("FCI", "F1")], delay_db["SLICE"][("FCI", "FCO")])
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carry1_delays[("FCI", "FCO")] = (0, 0)
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split_cells["TRELLIS_COMB_CARRY1"] = carry1_delays
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for celltype, celldelays in sorted(split_cells.items()):
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delays = []
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setupholds = []
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for (from_pin, to_pin), (min_delay, max_delay) in sorted(celldelays.items()):
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delays.append((constids[from_pin], constids[to_pin], min_delay, max_delay))
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cells.append((constids[celltype], delays, setupholds))
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def process_timing_data(family):
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for grade in speed_grade_names[family]:
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with open(timing_dbs.cells_db_path(family, grade)) as f:
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cell_data = json.load(f)
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cells = []
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for cell, cdata in sorted(cell_data.items()):
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celltype = constids[cell.replace(":", "_").replace("=", "_").replace(",", "_")]
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delays = []
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setupholds = []
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delay_db[cell] = {}
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for entry in cdata:
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if entry["type"] == "Width":
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continue
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elif entry["type"] == "IOPath":
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from_pin = entry["from_pin"][1] if type(entry["from_pin"]) is list else entry["from_pin"]
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if from_pin in timing_port_xform:
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from_pin = timing_port_xform[from_pin]
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to_pin = entry["to_pin"]
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if to_pin in timing_port_xform:
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to_pin = timing_port_xform[to_pin]
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min_delay = min(entry["rising"][0], entry["falling"][0])
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max_delay = min(entry["rising"][2], entry["falling"][2])
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delay_db[cell][(from_pin, to_pin)] = (min_delay, max_delay)
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delays.append((constids[from_pin], constids[to_pin], min_delay, max_delay))
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elif entry["type"] == "SetupHold":
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if type(entry["pin"]) is list:
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continue
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pin = constids[entry["pin"]]
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clock = constids[entry["clock"][1]]
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min_setup = entry["setup"][0]
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max_setup = entry["setup"][2]
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min_hold = entry["hold"][0]
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max_hold = entry["hold"][2]
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setupholds.append((pin, clock, min_setup, max_setup, min_hold, max_hold))
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else:
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assert False, entry["type"]
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cells.append((celltype, delays, setupholds))
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postprocess_timing_data(cells)
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pip_class_delays = []
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for i in range(len(pip_class_to_idx)):
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pip_class_delays.append((50, 50, 0, 0))
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pip_class_delays[pip_class_to_idx["zero"]] = (0, 0, 0, 0)
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with open(timing_dbs.interconnect_db_path(family, grade)) as f:
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interconn_data = json.load(f)
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for pipclass, pipdata in sorted(interconn_data.items()):
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min_delay = pipdata["delay"][0] * 1.1
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max_delay = pipdata["delay"][2] * 1.1
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min_fanout = pipdata["fanout"][0]
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max_fanout = pipdata["fanout"][2]
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if grade == speed_grade_names[family][0]:
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pip_class_to_idx[pipclass] = len(pip_class_delays)
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pip_class_delays.append((min_delay, max_delay, min_fanout, max_fanout))
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else:
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if pipclass in pip_class_to_idx:
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pip_class_delays[pip_class_to_idx[pipclass]] = (min_delay, max_delay, min_fanout, max_fanout)
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speed_grade_cells[grade] = cells
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speed_grade_pips[grade] = pip_class_delays
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def get_pip_class(wire_from, wire_to):
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if "FCO" in wire_from or "FCI" in wire_to:
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return pip_class_to_idx["zero"]
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if "F5" in wire_from or "FX" in wire_from or "FXA" in wire_to or "FXB" in wire_to:
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return pip_class_to_idx["zero"]
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if "JCLK" in wire_from:
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wire_from = wire_from.replace("JCLK","CLK")
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class_name = pip_classes.get_pip_class(wire_from, wire_to)
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if class_name is None or class_name not in pip_class_to_idx:
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class_name = "default"
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return pip_class_to_idx[class_name]
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def write_database(family, dev_name, chip, rg, endianness):
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def write_loc(loc, sym_name):
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bba.u16(loc.x, "%s.x" % sym_name)
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bba.u16(loc.y, "%s.y" % sym_name)
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# Use Lattice naming conventions, so convert to 1-based col indexing.
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def get_wire_name(loc, idx):
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tile = rg.tiles[loc]
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return "R{}C{}_{}".format(loc.y, loc.x + 1, rg.to_str(tile.wires[idx].name))
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# Before doing anything, ensure sorted routing graph iteration matches
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# y, x
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loc_iter = list(sorted(rg.tiles, key=lambda l : (l.y, l.x)))
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i = 1 # Drop (-2, -2) location.
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for y in range(0, max_row+1):
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for x in range(0, max_col+1):
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l = loc_iter[i]
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assert((y, x) == (l.y, l.x))
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i = i + 1
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bba = BinaryBlobAssembler()
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bba.pre('#include "nextpnr.h"')
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bba.pre('#include "embed.h"')
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bba.pre('NEXTPNR_NAMESPACE_BEGIN')
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bba.post('EmbeddedFile chipdb_file_%s("machxo2/chipdb-%s.bin", chipdb_blob_%s);' % (dev_name, dev_name, dev_name))
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bba.post('NEXTPNR_NAMESPACE_END')
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bba.push("chipdb_blob_%s" % args.device)
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bba.r("chip_info", "chip_info")
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# Nominally should be in order, but support situations where python
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# decides to iterate over rg.tiles out-of-order.
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for l in loc_iter:
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t = rg.tiles[l]
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# Do not include special globals location for now.
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if (l.x, l.y) == (-2, -2):
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continue
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if len(t.arcs) > 0:
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bba.l("loc%d_%d_pips" % (l.y, l.x), "PipInfoPOD")
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for arc in t.arcs:
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write_loc(arc.srcWire.rel, "src")
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write_loc(arc.sinkWire.rel, "dst")
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bba.u16(arc.srcWire.id, "src_idx {}".format(get_wire_name(arc.srcWire.rel, arc.srcWire.id)))
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bba.u16(arc.sinkWire.id, "dst_idx {}".format(get_wire_name(arc.sinkWire.rel, arc.sinkWire.id)))
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src_name = get_wire_name(arc.srcWire.rel, arc.srcWire.id)
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snk_name = get_wire_name(arc.sinkWire.rel, arc.sinkWire.id)
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bba.u16(get_pip_class(src_name, snk_name), "timing_class")
|
|
bba.u8(get_tiletype_index(rg.to_str(arc.tiletype)), "tile_type")
|
|
cls = arc.cls
|
|
bba.u8(cls, "pip_type")
|
|
bba.u16(arc.lutperm_flags, "lutperm_flags")
|
|
bba.u16(0, "padding")
|
|
|
|
if len(t.wires) > 0:
|
|
for wire_idx in range(len(t.wires)):
|
|
wire = t.wires[wire_idx]
|
|
if len(wire.arcsDownhill) > 0:
|
|
bba.l("loc%d_%d_wire%d_downpips" % (l.y, l.x, wire_idx), "PipLocatorPOD")
|
|
for dp in wire.arcsDownhill:
|
|
write_loc(dp.rel, "rel_loc")
|
|
bba.u32(dp.id, "index")
|
|
if len(wire.arcsUphill) > 0:
|
|
bba.l("loc%d_%d_wire%d_uppips" % (l.y, l.x, wire_idx), "PipLocatorPOD")
|
|
for up in wire.arcsUphill:
|
|
write_loc(up.rel, "rel_loc")
|
|
bba.u32(up.id, "index")
|
|
if len(wire.belPins) > 0:
|
|
bba.l("loc%d_%d_wire%d_belpins" % (l.y, l.x, wire_idx), "BelPortPOD")
|
|
for bp in wire.belPins:
|
|
write_loc(bp.bel.rel, "rel_bel_loc")
|
|
bba.u32(bp.bel.id, "bel_index")
|
|
bba.u32(constids[rg.to_str(bp.pin)], "port")
|
|
|
|
bba.l("loc%d_%d_wires" % (l.y, l.x), "WireInfoPOD")
|
|
for wire_idx in range(len(t.wires)):
|
|
wire = t.wires[wire_idx]
|
|
bba.s(rg.to_str(wire.name), "name")
|
|
bba.u16(constids[wire_type(rg.to_str(wire.name))], "type")
|
|
if ("TILE_WIRE_" + rg.to_str(wire.name)) in gfx_wire_ids:
|
|
bba.u16(gfx_wire_ids["TILE_WIRE_" + rg.to_str(wire.name)], "tile_wire")
|
|
else:
|
|
bba.u16(0, "tile_wire")
|
|
bba.r_slice("loc%d_%d_wire%d_uppips" % (l.y, l.x, wire_idx) if len(wire.arcsUphill) > 0 else None, len(wire.arcsUphill), "pips_uphill")
|
|
bba.r_slice("loc%d_%d_wire%d_downpips" % (l.y, l.x, wire_idx) if len(wire.arcsDownhill) > 0 else None, len(wire.arcsDownhill), "pips_downhill")
|
|
bba.r_slice("loc%d_%d_wire%d_belpins" % (l.y, l.x, wire_idx) if len(wire.belPins) > 0 else None, len(wire.belPins), "bel_pins")
|
|
|
|
if len(t.bels) > 0:
|
|
for bel_idx in range(len(t.bels)):
|
|
bel = t.bels[bel_idx]
|
|
bba.l("loc%d_%d_bel%d_wires" % (l.y, l.x, bel_idx), "BelWirePOD")
|
|
for pin in bel.wires:
|
|
write_loc(pin.wire.rel, "rel_wire_loc")
|
|
bba.u32(pin.wire.id, "wire_index")
|
|
bba.u32(constids[rg.to_str(pin.pin)], "port")
|
|
bba.u32(int(pin.dir), "type")
|
|
bba.l("loc%d_%d_bels" % (l.y, l.x), "BelInfoPOD")
|
|
for bel_idx in range(len(t.bels)):
|
|
bel = t.bels[bel_idx]
|
|
bba.s(rg.to_str(bel.name), "name")
|
|
bba.u32(constids[rg.to_str(bel.type)], "type")
|
|
bba.u32(bel.z, "z")
|
|
bba.r_slice("loc%d_%d_bel%d_wires" % (l.y, l.x, bel_idx), len(bel.wires), "bel_wires")
|
|
|
|
bba.l("tiles", "TileTypePOD")
|
|
for l in loc_iter:
|
|
t = rg.tiles[l]
|
|
|
|
if (l.y, l.x) == (-2, -2):
|
|
continue
|
|
|
|
bba.r_slice("loc%d_%d_bels" % (l.y, l.x) if len(t.bels) > 0 else None, len(t.bels), "bel_data")
|
|
bba.r_slice("loc%d_%d_wires" % (l.y, l.x) if len(t.wires) > 0 else None, len(t.wires), "wire_data")
|
|
bba.r_slice("loc%d_%d_pips" % (l.y, l.x) if len(t.arcs) > 0 else None, len(t.arcs), "pips_data")
|
|
|
|
for y in range(0, max_row+1):
|
|
for x in range(0, max_col+1):
|
|
bba.l("tile_info_%d_%d" % (x, y), "TileNamePOD")
|
|
for tile in chip.get_tiles_by_position(y, x):
|
|
bba.s(tile.info.name, "name")
|
|
bba.u16(get_tiletype_index(tile.info.type), "type_idx")
|
|
bba.u16(0, "padding")
|
|
|
|
bba.l("tiles_info", "TileInfoPOD")
|
|
for y in range(0, max_row+1):
|
|
for x in range(0, max_col+1):
|
|
bba.r_slice("tile_info_%d_%d" % (x, y), len(chip.get_tiles_by_position(y, x)), "tile_names")
|
|
|
|
for package, pkgdata in sorted(packages.items()):
|
|
bba.l("package_data_%s" % package, "PackagePinPOD")
|
|
for pin in pkgdata:
|
|
name, loc, bel_idx = pin
|
|
bba.s(name, "name")
|
|
write_loc(loc, "abs_loc")
|
|
bba.u32(bel_idx, "bel_index")
|
|
|
|
bba.l("package_data", "PackageInfoPOD")
|
|
for package, pkgdata in sorted(packages.items()):
|
|
bba.s(package, "name")
|
|
bba.r_slice("package_data_%s" % package, len(pkgdata), "pin_data")
|
|
|
|
bba.l("pio_info", "PIOInfoPOD")
|
|
for pin in pindata:
|
|
loc, bel_idx, bank, func, dqs = pin
|
|
write_loc(loc, "abs_loc")
|
|
bba.u32(bel_idx, "bel_index")
|
|
if func is not None and func != "WRITEN":
|
|
bba.s(func, "function_name")
|
|
else:
|
|
bba.r(None, "function_name")
|
|
# TODO: io_grouping? And DQS.
|
|
bba.u16(bank, "bank")
|
|
bba.u16(dqs, "dqsgroup")
|
|
|
|
bba.l("tiletype_names", "RelPtr<char>")
|
|
for tt, idx in sorted(tiletype_names.items(), key=lambda x: x[1]):
|
|
bba.s(tt, "name")
|
|
|
|
for grade in speed_grade_names[family]:
|
|
for cell in speed_grade_cells[grade]:
|
|
celltype, delays, setupholds = cell
|
|
if len(delays) > 0:
|
|
bba.l("cell_%d_delays_%s" % (celltype, grade))
|
|
for delay in delays:
|
|
from_pin, to_pin, min_delay, max_delay = delay
|
|
bba.u32(from_pin, "from_pin")
|
|
bba.u32(to_pin, "to_pin")
|
|
bba.u32(min_delay, "min_delay")
|
|
bba.u32(max_delay, "max_delay")
|
|
if len(setupholds) > 0:
|
|
bba.l("cell_%d_setupholds_%s" % (celltype, grade))
|
|
for sh in setupholds:
|
|
pin, clock, min_setup, max_setup, min_hold, max_hold = sh
|
|
bba.u32(pin, "sig_port")
|
|
bba.u32(clock, "clock_port")
|
|
bba.u32(min_setup, "min_setup")
|
|
bba.u32(max_setup, "max_setup")
|
|
bba.u32(min_hold, "min_hold")
|
|
bba.u32(max_hold, "max_hold")
|
|
bba.l("cell_timing_data_%s" % grade)
|
|
for cell in speed_grade_cells[grade]:
|
|
celltype, delays, setupholds = cell
|
|
bba.u32(celltype, "cell_type")
|
|
bba.r_slice("cell_%d_delays_%s" % (celltype, grade) if len(delays) > 0 else None, len(delays), "delays")
|
|
bba.r_slice("cell_%d_setupholds_%s" % (celltype, grade) if len(delays) > 0 else None, len(setupholds), "setupholds")
|
|
bba.l("pip_timing_data_%s" % grade)
|
|
for pipclass in speed_grade_pips[grade]:
|
|
min_delay, max_delay, min_fanout, max_fanout = pipclass
|
|
bba.u32(min_delay, "min_delay")
|
|
bba.u32(max_delay, "max_delay")
|
|
bba.u32(min_fanout, "min_fanout")
|
|
bba.u32(max_fanout, "max_fanout")
|
|
bba.l("speed_grade_data")
|
|
for grade in speed_grade_names[family]:
|
|
bba.r_slice("cell_timing_data_%s" % grade, len(speed_grade_cells[grade]), "cell_timings")
|
|
bba.r_slice("pip_timing_data_%s" % grade, len(speed_grade_pips[grade]), "pip_classes")
|
|
|
|
for name, var_data in sorted(variants.items()):
|
|
bba.l("supported_packages_%s" % name, "PackageSupportedPOD")
|
|
for package in var_data["packages"]:
|
|
bba.s(package, "name")
|
|
bba.s(package_shortname(package, chip.info.family), "short_name")
|
|
bba.l("supported_speed_grades_%s" % name, "SpeedSupportedPOD")
|
|
for speed in var_data["speeds"]:
|
|
bba.u16(speed, "speed")
|
|
bba.u16(speed_grade_names[family].index(str(speed)), "index")
|
|
bba.l("supported_suffixes_%s" % name, "SuffixeSupportedPOD")
|
|
for suffix in var_data["suffixes"]:
|
|
bba.s(suffix, "suffix")
|
|
|
|
bba.l("variant_data", "VariantInfoPOD")
|
|
for name, var_data in sorted(variants.items()):
|
|
bba.s(name, "variant_name")
|
|
bba.r_slice("supported_packages_%s" % name, len(var_data["packages"]), "supported_packages")
|
|
bba.r_slice("supported_speed_grades_%s" % name, len(var_data["speeds"]), "supported_speed_grades")
|
|
bba.r_slice("supported_suffixes_%s" % name, len(var_data["suffixes"]), "supported_suffixes")
|
|
|
|
bba.l("spine_info", "SpineInfoPOD")
|
|
spines = chip.global_data_machxo2.spines
|
|
for spine in spines:
|
|
bba.u32(spine.row, "row")
|
|
|
|
bba.l("chip_info")
|
|
bba.s(chip.info.family, "family")
|
|
bba.s(chip.info.name, "device_name")
|
|
bba.u32(max_col + 1, "width")
|
|
bba.u32(max_row + 1, "height")
|
|
bba.u32((max_col + 1) * (max_row + 1), "num_tiles")
|
|
bba.u32(const_id_count, "const_id_count")
|
|
|
|
bba.r_slice("tiles", (max_col + 1) * (max_row + 1), "tiles")
|
|
bba.r_slice("tiletype_names", len(tiletype_names), "tiletype_names")
|
|
bba.r_slice("package_data", len(packages), "package_info")
|
|
bba.r_slice("pio_info", len(pindata), "pio_info")
|
|
bba.r_slice("tiles_info", (max_col + 1) * (max_row + 1), "tile_info")
|
|
bba.r_slice("variant_data", len(variants), "variant_info")
|
|
bba.r_slice("spine_info", len(spines), "spine_info")
|
|
bba.r_slice("speed_grade_data", len(speed_grade_names[family]), "speed_grades")
|
|
|
|
bba.pop()
|
|
return bba
|
|
|
|
|
|
dev_family = {
|
|
"256X": "MachXO",
|
|
"640X": "MachXO",
|
|
"1200X":"MachXO",
|
|
"2280X":"MachXO",
|
|
|
|
"256": "MachXO2",
|
|
"640": "MachXO2",
|
|
"1200": "MachXO2",
|
|
"2000": "MachXO2",
|
|
"4000": "MachXO2",
|
|
"7000": "MachXO2",
|
|
|
|
"1300": "MachXO3",
|
|
"2100": "MachXO3",
|
|
"4300": "MachXO3",
|
|
"6900": "MachXO3",
|
|
"9400": "MachXO3",
|
|
|
|
"4300D": "MachXO3D",
|
|
"9400D": "MachXO3D"
|
|
}
|
|
|
|
dev_names = {
|
|
"256X": "LCMXO256",
|
|
"640X": "LCMXO640",
|
|
"1200X":"LCMXO1200",
|
|
"2280X":"LCMXO2280",
|
|
|
|
"256": "LCMXO2-256",
|
|
"640": "LCMXO2-640",
|
|
"1200": "LCMXO2-1200",
|
|
"2000": "LCMXO2-2000",
|
|
"4000": "LCMXO2-4000",
|
|
"7000": "LCMXO2-7000",
|
|
|
|
"1300": "LCMXO3-1300",
|
|
"2100": "LCMXO3-2100",
|
|
"4300": "LCMXO3-4300",
|
|
"6900": "LCMXO3-6900",
|
|
"9400": "LCMXO3-9400",
|
|
|
|
"4300D": "LCMXO3D-4300",
|
|
"9400D": "LCMXO3D-9400"
|
|
}
|
|
|
|
def main():
|
|
global max_row, max_col, const_id_count
|
|
|
|
pytrellis.load_database(database.get_db_root())
|
|
args = parser.parse_args()
|
|
|
|
const_id_count = 1 # count ID_NONE
|
|
with open(args.constids) as f:
|
|
for line in f:
|
|
line = line.replace("(", " ")
|
|
line = line.replace(")", " ")
|
|
line = line.split()
|
|
if len(line) == 0:
|
|
continue
|
|
assert len(line) == 2
|
|
assert line[0] == "X"
|
|
idx = len(constids) + 1
|
|
constids[line[1]] = idx
|
|
const_id_count += 1
|
|
|
|
constids["SLICE"] = constids["TRELLIS_SLICE"]
|
|
constids["PIO"] = constids["TRELLIS_IO"]
|
|
|
|
chip = pytrellis.Chip(dev_names[args.device])
|
|
rg = pytrellis.make_optimized_chipdb(chip, include_lutperm_pips=True, split_slice_mode=True)
|
|
max_row = chip.get_max_row()
|
|
max_col = chip.get_max_col()
|
|
process_timing_data(dev_family[args.device])
|
|
process_pio_db(rg, args.device)
|
|
process_devices_db(chip.info.family, chip.info.name)
|
|
bba = write_database(dev_family[args.device],args.device, chip, rg, "le")
|
|
|
|
|
|
|
|
if __name__ == "__main__":
|
|
main()
|