517 lines
21 KiB
C++
517 lines
21 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "design_utils.h"
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#include "log.h"
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#include "nextpnr.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace {
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struct MistralPacker
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{
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MistralPacker(Context *ctx) : ctx(ctx) {};
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Context *ctx;
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NetInfo *gnd_net, *vcc_net;
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void init_constant_nets()
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{
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CellInfo *gnd_drv = ctx->createCell(ctx->id("$PACKER_GND_DRV"), id_MISTRAL_CONST);
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gnd_drv->params[id_LUT] = 0;
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gnd_drv->addOutput(id_Q);
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CellInfo *vcc_drv = ctx->createCell(ctx->id("$PACKER_VCC_DRV"), id_MISTRAL_CONST);
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vcc_drv->params[id_LUT] = 1;
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vcc_drv->addOutput(id_Q);
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gnd_net = ctx->createNet(ctx->id("$PACKER_GND_NET"));
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vcc_net = ctx->createNet(ctx->id("$PACKER_VCC_NET"));
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gnd_drv->connectPort(id_Q, gnd_net);
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vcc_drv->connectPort(id_Q, vcc_net);
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}
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CellPinState get_pin_needed_muxval(CellInfo *cell, IdString port)
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{
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NetInfo *net = cell->getPort(port);
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if (net == nullptr || net->driver.cell == nullptr) {
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// Pin is disconnected
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// If a mux value exists already, honour it
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CellPinState exist_mux = cell->get_pin_state(port);
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if (exist_mux != PIN_SIG)
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return exist_mux;
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// Otherwise, look up the default value and use that
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CellPinStyle pin_style = ctx->get_cell_pin_style(cell, port);
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if ((pin_style & PINDEF_MASK) == PINDEF_0)
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return PIN_0;
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else if ((pin_style & PINDEF_MASK) == PINDEF_1)
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return PIN_1;
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else
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return PIN_SIG;
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}
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// Look to see if the driver is an inverter or constant
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IdString drv_type = net->driver.cell->type;
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if (drv_type == id_MISTRAL_NOT)
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return PIN_INV;
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else if (drv_type == id_GND)
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return PIN_0;
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else if (drv_type == id_VCC)
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return PIN_1;
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else
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return PIN_SIG;
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}
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void uninvert_port(CellInfo *cell, IdString port)
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{
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// Rewire a port so it is driven by the input to an inverter
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NetInfo *net = cell->getPort(port);
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NPNR_ASSERT(net != nullptr && net->driver.cell != nullptr && net->driver.cell->type == id_MISTRAL_NOT);
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CellInfo *inv = net->driver.cell;
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cell->disconnectPort(port);
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NetInfo *inv_a = inv->getPort(id_A);
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if (inv_a != nullptr) {
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cell->connectPort(port, inv_a);
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}
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}
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void process_inv_constants(CellInfo *cell)
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{
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// TODO: we might need to create missing inputs here in some cases so we can tie them to the correct constant?
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// Fold inverters and constants into a cell
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for (auto &port : cell->ports) {
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// Iterate over all inputs
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if (port.second.type != PORT_IN)
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continue;
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IdString port_name = port.first;
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CellPinState req_mux = get_pin_needed_muxval(cell, port_name);
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if (req_mux == PIN_SIG) {
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// No special setting required, ignore
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continue;
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}
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CellPinStyle pin_style = ctx->get_cell_pin_style(cell, port_name);
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if (req_mux == PIN_INV) {
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// Pin is inverted. If there is a hard inverter; then use it
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if (pin_style & PINOPT_INV) {
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uninvert_port(cell, port_name);
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cell->pin_data[port_name].state = PIN_INV;
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}
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} else if (req_mux == PIN_0 || req_mux == PIN_1) {
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// Pin is tied to a constant
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// If there is a hard constant option; use it
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if ((pin_style & int(req_mux)) == req_mux) {
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cell->disconnectPort(port_name);
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cell->pin_data[port_name].state = req_mux;
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} else {
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cell->disconnectPort(port_name);
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// There is no hard constant, we need to connect it to the relevant soft-constant net
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cell->connectPort(port_name, (req_mux == PIN_1) ? vcc_net : gnd_net);
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}
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}
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}
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}
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void trim_design()
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{
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// Remove unused inverters and high/low drivers
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std::vector<IdString> trim_cells;
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std::vector<IdString> trim_nets;
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (ci->type != id_MISTRAL_NOT && ci->type != id_GND && ci->type != id_VCC)
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continue;
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IdString port = (ci->type == id_MISTRAL_NOT) ? id_Q : id_Y;
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NetInfo *out = ci->getPort(port);
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if (out == nullptr) {
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trim_cells.push_back(ci->name);
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continue;
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}
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if (!out->users.empty())
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continue;
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ci->disconnectPort(id_A);
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trim_cells.push_back(ci->name);
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trim_nets.push_back(out->name);
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}
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for (IdString rem_net : trim_nets)
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ctx->nets.erase(rem_net);
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for (IdString rem_cell : trim_cells)
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ctx->cells.erase(rem_cell);
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}
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void pack_constants()
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{
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// Iterate through cells
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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// Skip certain cells at this point
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if (ci->type != id_MISTRAL_NOT && ci->type != id_GND && ci->type != id_VCC)
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process_inv_constants(ci);
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}
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// Special case - SDATA can only be trimmed if SLOAD is low
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (ci->type != id_MISTRAL_FF)
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continue;
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if (ci->get_pin_state(id_SLOAD) != PIN_0)
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continue;
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ci->disconnectPort(id_SDATA);
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}
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// Remove superfluous inverters and constant drivers
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trim_design();
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}
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void prepare_io()
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{
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// Find the actual IO buffer corresponding to a port; and copy attributes across to it
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// Note that this relies on Yosys to do IO buffer inference, to avoid tristate issues once we get to synthesised
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// JSON. In all cases the nextpnr-inserted IO buffers are removed as redundant.
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for (auto &port : ctx->ports) {
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if (!ctx->cells.count(port.first))
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log_error("Port '%s' doesn't seem to have a corresponding top level IO\n", ctx->nameOf(port.first));
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CellInfo *ci = ctx->cells.at(port.first).get();
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PortRef top_port;
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top_port.cell = nullptr;
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bool is_npnr_iob = false;
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if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
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// Might have an input buffer (IB etc) connected to it
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is_npnr_iob = true;
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NetInfo *o = ci->getPort(id_O);
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if (o == nullptr)
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;
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else if (o->users.entries() > 1)
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log_error("Top level pin '%s' has multiple input buffers\n", ctx->nameOf(port.first));
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else if (o->users.entries() == 1)
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top_port = *o->users.begin();
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}
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if (ci->type == ctx->id("$nextpnr_obuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
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// Might have an output buffer (OB etc) connected to it
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is_npnr_iob = true;
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NetInfo *i = ci->getPort(id_I);
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if (i != nullptr && i->driver.cell != nullptr) {
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if (top_port.cell != nullptr)
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log_error("Top level pin '%s' has multiple input/output buffers\n", ctx->nameOf(port.first));
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top_port = i->driver;
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}
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// Edge case of a bidirectional buffer driving an output pin
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if (i->users.entries() > 2) {
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log_error("Top level pin '%s' has illegal buffer configuration\n", ctx->nameOf(port.first));
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} else if (i->users.entries() == 2) {
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if (top_port.cell != nullptr)
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log_error("Top level pin '%s' has illegal buffer configuration\n", ctx->nameOf(port.first));
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for (auto &usr : i->users) {
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if (usr.cell->type == ctx->id("$nextpnr_obuf") || usr.cell->type == ctx->id("$nextpnr_iobuf"))
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continue;
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top_port = usr;
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break;
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}
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}
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}
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if (!is_npnr_iob)
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log_error("Port '%s' doesn't seem to have a corresponding top level IO (internal cell type mismatch)\n",
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ctx->nameOf(port.first));
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if (top_port.cell == nullptr) {
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log_info("Trimming port '%s' as it is unused.\n", ctx->nameOf(port.first));
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} else {
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// Copy attributes to real IO buffer
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if (ctx->io_attr.count(port.first)) {
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for (auto &kv : ctx->io_attr.at(port.first)) {
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top_port.cell->attrs[kv.first] = kv.second;
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}
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}
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// Make sure that top level net is set correctly
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port.second.net = top_port.cell->ports.at(top_port.port).net;
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}
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// Now remove the nextpnr-inserted buffer
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ci->disconnectPort(id_I);
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ci->disconnectPort(id_O);
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ctx->cells.erase(port.first);
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}
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}
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void pack_io()
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{
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// Step 0: deal with top level inserted IO buffers
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prepare_io();
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// Stage 1: apply constraints
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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// Iterate through all IO buffer primitives
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if (!ctx->is_io_cell(ci->type))
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continue;
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// We need all IO constrained at the moment, unconstrained IO are rare enough not to care
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if (!ci->attrs.count(id_LOC))
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log_error("Found unconstrained IO '%s', these are currently unsupported\n", ctx->nameOf(ci));
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// Convert package pin constraint to bel constraint
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std::string loc = ci->attrs.at(id_LOC).as_string();
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if (loc.compare(0, 4, "PIN_") != 0)
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log_error("Expecting PIN_-prefixed pin for IO '%s', got '%s'\n", ctx->nameOf(ci), loc.c_str());
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auto pin_info = ctx->cyclonev->pin_find_name(loc.substr(4));
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if (pin_info == nullptr)
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log_error("IO '%s' is constrained to invalid pin '%s'\n", ctx->nameOf(ci), loc.c_str());
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BelId bel = ctx->get_io_pin_bel(pin_info);
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if (bel == BelId()) {
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log_error("IO '%s' is constrained to pin %s which is not a supported IO pin.\n", ctx->nameOf(ci),
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loc.c_str());
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} else {
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log_info("Constraining IO '%s' to pin %s (bel %s)\n", ctx->nameOf(ci), loc.c_str(),
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ctx->nameOfBel(bel));
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ctx->bindBel(bel, ci, STRENGTH_LOCKED);
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}
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}
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}
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void constrain_carries()
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{
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (ci->type != id_MISTRAL_ALUT_ARITH)
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continue;
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const NetInfo *cin = ci->getPort(id_CI);
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if (cin != nullptr && cin->driver.cell != nullptr)
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continue; // not the start of a chain
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std::vector<CellInfo *> chain;
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CellInfo *cursor = ci;
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while (true) {
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chain.push_back(cursor);
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const NetInfo *co = cursor->getPort(id_CO);
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if (co == nullptr || co->users.empty())
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break;
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if (co->users.entries() > 1)
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log_error("Carry net %s has more than one sink!\n", ctx->nameOf(co));
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auto &usr = *co->users.begin();
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if (usr.port != id_CI)
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log_error("Carry net %s drives port %s, expected CI\n", ctx->nameOf(co), ctx->nameOf(usr.port));
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cursor = usr.cell;
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}
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chain.at(0)->constr_abs_z = true;
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chain.at(0)->constr_z = 0;
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chain.at(0)->cluster = chain.at(0)->name;
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for (int i = 1; i < int(chain.size()); i++) {
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chain.at(i)->constr_x = 0;
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chain.at(i)->constr_y = -(i / 20);
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// 2 COMB, 4 FF per ALM
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chain.at(i)->constr_z = ((i / 2) % 10) * 6 + (i % 2);
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chain.at(i)->constr_abs_z = true;
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chain.at(i)->cluster = chain.at(0)->name;
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chain.at(0)->constr_children.push_back(chain.at(i));
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}
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if (ctx->debug) {
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log_info("Chain: \n");
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for (int i = 0; i < int(chain.size()); i++) {
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auto &c = chain.at(i);
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log_info(" i=%d cell=%s dy=%d z=%d ci=%s co=%s\n", i, ctx->nameOf(c), c->constr_y, c->constr_z,
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ctx->nameOf(c->getPort(id_CI)), ctx->nameOf(c->getPort(id_CO)));
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}
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}
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}
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// Check we reached all the cells in the above pass
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (ci->type != id_MISTRAL_ALUT_ARITH)
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continue;
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if (ci->cluster == ClusterId())
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log_error("Failed to include arith cell '%s' in any chain (CI=%s)\n", ctx->nameOf(ci),
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ctx->nameOf(ci->getPort(id_CI)));
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}
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}
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void constrain_lutram()
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{
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// We form clusters based on both read and write address; as both being the same makes it more likely these
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// cells should be packed together, too.
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// This makes things easier for the placement legaliser to deal with RAM in LAB-compatible blocks without
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// over-constraining things
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idict<dict<IdString, IdString>> mlab_keys;
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std::vector<std::vector<CellInfo *>> mlab_groups;
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (ci->type != id_MISTRAL_MLAB)
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continue;
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auto key = ctx->get_mlab_key(ci, true);
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int key_idx = mlab_keys(key);
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if (key_idx >= int(mlab_groups.size()))
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mlab_groups.resize(key_idx + 1);
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mlab_groups.at(key_idx).push_back(ci);
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}
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// Combine into clusters
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size_t cluster_size = 20;
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for (auto &group : mlab_groups) {
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for (size_t i = 0; i < group.size(); i++) {
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CellInfo *ci = group.at(i);
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CellInfo *base = group.at((i / cluster_size) * cluster_size);
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int cell_index = int(i) % cluster_size;
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int alm = cell_index / 2;
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int alm_cell = cell_index % 2;
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ci->cluster = base->name;
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ci->constr_abs_z = true;
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ci->constr_z = alm * 6 + alm_cell;
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if (cell_index != 0) {
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// Not the root of a cluster
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base->constr_children.push_back(ci);
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ci->constr_x = 0;
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ci->constr_y = 0;
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}
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}
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}
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}
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void setup_m10ks()
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{
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (ci->type != id_MISTRAL_M10K)
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continue;
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auto abits = ci->params.at(id_CFG_ABITS).as_int64();
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auto dbits = ci->params.at(id_CFG_DBITS).as_int64();
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NPNR_ASSERT(abits >= 7 && abits <= 13);
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NPNR_ASSERT(dbits == 1 || dbits == 2 || dbits == 5 || dbits == 10 || dbits == 20 || dbits == 40);
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NPNR_ASSERT((1 << abits) * dbits <= 10240);
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log_info("Setting up %ld-bit address, %ld-bit data M10K for %s.\n", abits, dbits,
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ci->name.str(ctx).c_str());
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// Quartus doesn't seem to generate ADDRSTALL[AB], BYTEENABLE[AB][01].
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// It *does* generate ACLR[01] but leaves them unconnected if unused.
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// Enables.
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// RDEN[1] is left unconnected.
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if (dbits == 40)
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ci->pin_data[ctx->id("A1EN")].bel_pins = {ctx->id("WREN[0]")};
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else
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ci->pin_data[ctx->id("A1EN")].bel_pins = {ctx->id("WREN[1]")};
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ci->pin_data[ctx->id("B1EN")].bel_pins = {ctx->id("RDEN[0]")};
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// Clocks.
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ci->pin_data[ctx->id("CLK1")].bel_pins = {ctx->id("CLKIN[0]")};
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// Enables left unconnected.
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// Address lines.
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// One could remove the std::max here and the `- bit_offset`s here,
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// because they would cancel out, but I think this way is less confusing.
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int addr_offset = std::max(12 - std::max(abits, dbits == 40 ? 8L : 9L), 0L);
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int bit_offset = (abits == 13);
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if (abits == 13) {
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ci->pin_data[ctx->id("A1ADDR[0]")].bel_pins = {ctx->id("DATAAIN[4]")};
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ci->pin_data[ctx->id("B1ADDR[0]")].bel_pins = {ctx->id("DATABIN[19]")};
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}
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for (int bit = bit_offset; bit < abits; bit++) {
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ci->pin_data[ctx->idf("A1ADDR[%d]", bit)].bel_pins = {
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ctx->idf("ADDRA[%d]", bit + addr_offset - bit_offset)};
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ci->pin_data[ctx->idf("B1ADDR[%d]", bit)].bel_pins = {
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ctx->idf("ADDRB[%d]", bit + addr_offset - bit_offset)};
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}
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// Data lines
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std::vector<int> offsets;
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offsets.push_back(0);
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if (abits >= 10 && dbits <= 10) {
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offsets.push_back(10);
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}
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if (abits >= 11 && dbits <= 5) {
|
|
offsets.push_back(5);
|
|
offsets.push_back(15);
|
|
}
|
|
if (abits >= 12 && dbits <= 2) {
|
|
offsets.push_back(2);
|
|
offsets.push_back(7);
|
|
offsets.push_back(12);
|
|
offsets.push_back(17);
|
|
}
|
|
if (abits == 13 && dbits == 1) {
|
|
offsets.push_back(1);
|
|
offsets.push_back(3);
|
|
offsets.push_back(6);
|
|
offsets.push_back(8);
|
|
offsets.push_back(11);
|
|
offsets.push_back(13);
|
|
offsets.push_back(16);
|
|
offsets.push_back(18);
|
|
}
|
|
|
|
// In this corner case the pin name does not have indexing
|
|
// because it's a single bit wide...
|
|
if (abits == 13 && dbits == 1) {
|
|
for (int offset : offsets)
|
|
ci->pin_data[ctx->idf("A1DATA")].bel_pins.push_back(ctx->idf("DATAAIN[%d]", offset));
|
|
ci->pin_data[ctx->idf("B1DATA")].bel_pins = {ctx->idf("DATABOUT[0]")};
|
|
continue;
|
|
}
|
|
|
|
// 40-bit data mode causes some headaches...
|
|
bit_offset = dbits == 40 ? 20 : 0;
|
|
|
|
// Write port
|
|
for (int bit = 0; bit < std::min(dbits, 20L); bit++)
|
|
for (int offset : offsets)
|
|
ci->pin_data[ctx->idf("A1DATA[%d]", bit)].bel_pins.push_back(ctx->idf("DATAAIN[%d]", bit + offset));
|
|
|
|
if (dbits == 40)
|
|
for (int bit = bit_offset; bit < dbits; bit++)
|
|
ci->pin_data[ctx->idf("A1DATA[%d]", bit)].bel_pins.push_back(
|
|
ctx->idf("DATABIN[%d]", bit - bit_offset));
|
|
|
|
// Read port
|
|
if (dbits == 40)
|
|
for (int bit = 0; bit < 20; bit++)
|
|
ci->pin_data[ctx->idf("B1DATA[%d]", bit)].bel_pins = {ctx->idf("DATAAOUT[%d]", bit)};
|
|
|
|
for (int bit = bit_offset; bit < dbits; bit++)
|
|
ci->pin_data[ctx->idf("B1DATA[%d]", bit)].bel_pins = {ctx->idf("DATABOUT[%d]", bit - bit_offset)};
|
|
}
|
|
}
|
|
|
|
void run()
|
|
{
|
|
init_constant_nets();
|
|
pack_constants();
|
|
pack_io();
|
|
constrain_carries();
|
|
constrain_lutram();
|
|
setup_m10ks();
|
|
}
|
|
};
|
|
}; // namespace
|
|
|
|
bool Arch::pack()
|
|
{
|
|
MistralPacker packer(getCtx());
|
|
packer.run();
|
|
|
|
assignArchInfo();
|
|
|
|
return true;
|
|
}
|
|
|
|
NEXTPNR_NAMESPACE_END
|