03c413a27a
Add processing IO located on the sides of some chips. These are IOBUF, which are converted into IBUF and OBUF not by fuses, but by signaling to OE. Also added the creation of a Global Set / Reset for all chips, instead of a list of tile types, information from the apicula database is used, and minor fixes. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
95 lines
2.9 KiB
C++
95 lines
2.9 KiB
C++
#ifndef GOWIN_H
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#define GOWIN_H
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#include "nextpnr.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace BelFlags {
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static constexpr uint32_t FLAG_SIMPLE_IO = 0x100;
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}
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namespace {
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// Return true if a cell is a LUT
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inline bool type_is_lut(IdString cell_type) { return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4); }
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inline bool is_lut(const CellInfo *cell) { return type_is_lut(cell->type); }
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// Return true if a cell is a DFF
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inline bool type_is_dff(IdString cell_type)
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{
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return cell_type.in(id_DFF, id_DFFE, id_DFFN, id_DFFNE, id_DFFS, id_DFFSE, id_DFFNS, id_DFFNSE, id_DFFR, id_DFFRE,
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id_DFFNR, id_DFFNRE, id_DFFP, id_DFFPE, id_DFFNP, id_DFFNPE, id_DFFC, id_DFFCE, id_DFFNC,
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id_DFFNCE);
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}
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inline bool is_dff(const CellInfo *cell) { return type_is_dff(cell->type); }
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// Return true if a cell is a ALU
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inline bool type_is_alu(IdString cell_type) { return cell_type == id_ALU; }
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inline bool is_alu(const CellInfo *cell) { return type_is_alu(cell->type); }
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// Return true if a cell is a SSRAM
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inline bool type_is_ssram(IdString cell_type) { return cell_type.in(id_RAM16SDP1, id_RAM16SDP2, id_RAM16SDP4); }
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inline bool is_ssram(const CellInfo *cell) { return type_is_ssram(cell->type); }
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// extra data in the chip db
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NPNR_PACKED_STRUCT(struct Bottom_io_cnd_POD {
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int32_t wire_a_net;
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int32_t wire_b_net;
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});
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NPNR_PACKED_STRUCT(struct Bottom_io_POD {
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// simple OBUF
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static constexpr int8_t NORMAL = 0;
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RelSlice<Bottom_io_cnd_POD> conditions;
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});
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NPNR_PACKED_STRUCT(struct Extra_chip_data_POD { Bottom_io_POD bottom_io; });
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inline bool have_bottom_io_cnds(const ChipInfoPOD *chip)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(chip->extra_data.get());
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return extra->bottom_io.conditions.size() != 0;
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}
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inline IdString get_bottom_io_wire_a_net(const ChipInfoPOD *chip, int8_t condition)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(chip->extra_data.get());
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return IdString(extra->bottom_io.conditions[condition].wire_a_net);
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}
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inline IdString get_bottom_io_wire_b_net(const ChipInfoPOD *chip, int8_t condition)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(chip->extra_data.get());
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return IdString(extra->bottom_io.conditions[condition].wire_b_net);
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}
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inline bool getBelSimpleIO(const ChipInfoPOD *chip, BelId bel)
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{
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return chip_bel_info(chip, bel).flags & BelFlags::FLAG_SIMPLE_IO;
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}
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} // namespace
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// Bels Z ranges. It is desirable that these numbers be synchronized with the chipdb generator
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namespace BelZ {
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enum
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{
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LUT0_Z = 0,
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LUT7_Z = 14,
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MUX20_Z = 16,
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MUX21_Z = 18,
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MUX23_Z = 22,
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MUX27_Z = 29,
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ALU0_Z = 30, // :35, 6 ALU
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RAMW_Z = 36, // RAM16SDP4
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IOBA_Z = 50,
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IOBB_Z = 51, // +IOBC...IOBL
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PLL_Z = 275,
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GSR_Z = 276,
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VCC_Z = 277,
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VSS_Z = 278
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};
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}
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NEXTPNR_NAMESPACE_END
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#endif
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