77ffdd7fd4
Also move all tests in a tests directory Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
9 lines
138 B
Verilog
9 lines
138 B
Verilog
module top(output o, output o2, output o3, output o4);
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assign o = 1'b0;
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assign o2 = 1'b1;
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assign o3 = 1'b0;
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assign o4 = 1'b1;
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endmodule
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