25 lines
436 B
Verilog
25 lines
436 B
Verilog
module top (
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input wire clk,
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input wire rx,
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output wire tx,
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input wire [15:0] sw,
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output wire [15:0] led
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);
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RAM128X1D #(
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.INIT(128'hFFEEDDCCBBAA99887766554433221100)
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) ram_i (
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.WCLK(clk),
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.A(sw[6:0]),
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.DPRA(sw[13:7]),
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.WE(sw[14]),
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.D(sw[15]),
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.SPO(led[0]),
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.DPO(led[1]),
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);
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assign led[15:2] = 14'b0;
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assign tx = rx;
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endmodule
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