124 lines
2.7 KiB
Verilog
124 lines
2.7 KiB
Verilog
module ram0(
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// Write port
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input wrclk,
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input [7:0] di,
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input wren,
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input [5:0] wraddr,
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// Read port
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input rdclk,
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input rden,
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input [5:0] rdaddr,
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output reg [7:0] do);
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(* syn_ramstyle = "block_ram" *) reg [7:0] ram[0:63];
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initial begin
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ram[0] = 8'b00000001;
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ram[1] = 8'b10101010;
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ram[2] = 8'b01010101;
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ram[3] = 8'b11111111;
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ram[4] = 8'b11110000;
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ram[5] = 8'b00001111;
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ram[6] = 8'b11001100;
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ram[7] = 8'b00110011;
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ram[8] = 8'b00000010;
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ram[9] = 8'b00000100;
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end
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always @ (posedge wrclk) begin
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if(wren == 1) begin
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ram[wraddr] <= di;
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end
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end
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always @ (posedge rdclk) begin
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if(rden == 1) begin
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do <= ram[rdaddr];
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end
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end
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endmodule
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module top (
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input wire clk,
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input wire pb0,
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input wire pb1,
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input wire [7:0] sw,
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output wire [13:0] led
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);
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wire bufclk;
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DCC gbuf_i(.CLKI(clk), .CLKO(bufclk));
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wire rden;
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reg wren;
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wire [5:0] rdaddr;
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wire [5:0] wraddr;
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wire [7:0] di;
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wire [7:0] do;
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ram0 ram(
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.wrclk(bufclk),
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.di(di),
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.wren(wren),
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.wraddr(wraddr),
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.rdclk(bufclk),
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.rden(rden),
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.rdaddr(rdaddr),
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.do(do)
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);
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reg [5:0] address_reg;
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reg [7:0] data_reg;
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reg [7:0] out_reg;
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assign rdaddr = address_reg;
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assign wraddr = address_reg;
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// input_mode == 00 -> in[3:0] -> address_reg
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// input_mode == 01 -> in[3:0] -> data_reg[3:0]
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// input_mode == 10 -> in[3:0] -> data_reg[7:4]
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// input_mode == 11 -> data_reg -> ram[address_reg]
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wire [1:0] input_mode;
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// WE == 0 -> address_reg and data_reg unchanged.
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// WE == 1 -> address_reg or data_reg is updated because on input_mode.
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wire we;
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assign input_mode[0] = ~sw[6];
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assign input_mode[1] = ~sw[7];
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assign we = ~pb0;
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assign led = ~{address_reg, out_reg};
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assign di = data_reg;
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assign rden = 1;
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initial begin
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wren = 1'b0;
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address_reg = 10'b0;
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data_reg = 16'b0;
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out_reg = 16'b0;
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end
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always @ (posedge bufclk) begin
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out_reg <= do;
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if(we == 1) begin
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if(input_mode == 0) begin
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address_reg <= ~sw[5:0];
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wren <= 0;
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end else if(input_mode == 1) begin
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data_reg[3:0] <= ~sw[3:0];
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wren <= 0;
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end else if(input_mode == 2) begin
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data_reg[7:4] <= ~sw[3:0];
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wren <= 0;
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end else if(input_mode == 3) begin
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wren <= 1;
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end
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end
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end
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endmodule
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