154 lines
5.1 KiB
C++
154 lines
5.1 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021 Lofty <dan.ravensloft@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef MISTRAL_ARCH_H
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#define MISTRAL_ARCH_H
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#include <set>
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#include <sstream>
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#include "base_arch.h"
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#include "nextpnr_types.h"
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#include "relptr.h"
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#include "cyclonev.h"
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NEXTPNR_NAMESPACE_BEGIN
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struct ArchArgs
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{
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std::string device;
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};
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struct PinInfo
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{
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IdString name;
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WireId wire;
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PortType type;
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};
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struct BelInfo
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{
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IdString name, type;
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std::map<IdString, std::string> attrs;
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CellInfo *bound_cell;
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std::unordered_map<IdString, PinInfo> pins;
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DecalXY decalxy;
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int x, y, z;
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bool gb;
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};
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struct ArchRanges : BaseArchRanges
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{
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using ArchArgsT = ArchArgs;
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// Bels
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using AllBelsRangeT = const std::vector<BelId> &;
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using TileBelsRangeT = std::vector<BelId>;
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using BelPinsRangeT = std::vector<IdString>;
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// Wires
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using AllWiresRangeT = const std::vector<WireId> &;
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using DownhillPipRangeT = const std::vector<PipId> &;
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using UphillPipRangeT = const std::vector<PipId> &;
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using WireBelPinRangeT = std::vector<BelPin>;
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// Pips
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using AllPipsRangeT = const std::vector<PipId> &;
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};
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struct Arch : BaseArch<ArchRanges>
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{
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ArchArgs args;
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mistral::CycloneV *cyclonev;
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std::unordered_map<BelId, BelInfo> bels;
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std::vector<BelId> bel_list;
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Arch(ArchArgs args);
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std::string getChipName() const override { return std::string{"TODO: getChipName"}; }
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// -------------------------------------------------
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int getGridDimX() const override { return cyclonev->get_tile_sx(); }
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int getGridDimY() const override { return cyclonev->get_tile_sy(); }
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int getTileBelDimZ(int x, int y) const override; // arch.cc
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// -------------------------------------------------
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BelId getBelByName(IdStringList name) const override; // arch.cc
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IdStringList getBelName(BelId bel) const override; // arch.cc
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const std::vector<BelId> &getBels() const override { return bel_list; }
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std::vector<BelId> getBelsByTile(int x, int y) const override;
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Loc getBelLocation(BelId bel) const override
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{
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return Loc(CycloneV::pos2x(bel.pos), CycloneV::pos2y(bel.pos), bel.z);
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}
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BelId getBelByLocation(Loc loc) const override { return BelId(CycloneV::xy2pos(loc.x, loc.y), loc.z); }
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IdString getBelType(BelId bel) const override; // arch.cc
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WireId getBelPinWire(BelId bel, IdString pin) const override;
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PortType getBelPinType(BelId bel, IdString pin) const override;
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std::vector<IdString> getBelPins(BelId bel) const override;
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// -------------------------------------------------
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WireId getWireByName(IdStringList name) const override;
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IdStringList getWireName(WireId wire) const override;
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DelayQuad getWireDelay(WireId wire) const;
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std::vector<BelPin> getWireBelPins(WireId wire) const override;
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const std::vector<WireId> &getWires() const override;
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// -------------------------------------------------
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PipId getPipByName(IdStringList name) const override;
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const std::vector<PipId> &getPips() const override;
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Loc getPipLocation(PipId pip) const override;
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IdStringList getPipName(PipId pip) const override;
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WireId getPipSrcWire(PipId pip) const override;
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WireId getPipDstWire(PipId pip) const override;
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DelayQuad getPipDelay(PipId pip) const override;
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const std::vector<PipId> &getPipsDownhill(WireId wire) const override;
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const std::vector<PipId> &getPipsUphill(WireId wire) const override;
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// -------------------------------------------------
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delay_t estimateDelay(WireId src, WireId dst) const override;
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delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override;
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delay_t getDelayEpsilon() const override;
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delay_t getRipupDelayPenalty() const override;
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float getDelayNS(delay_t v) const override;
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delay_t getDelayFromNS(float ns) const override;
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uint32_t getDelayChecksum(delay_t v) const override;
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ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
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// -------------------------------------------------
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bool pack() override;
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bool place() override;
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bool route() override;
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// -------------------------------------------------
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static const std::string defaultPlacer;
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static const std::vector<std::string> availablePlacers;
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static const std::string defaultRouter;
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static const std::vector<std::string> availableRouters;
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};
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NEXTPNR_NAMESPACE_END
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#endif |