865 lines
23 KiB
C++
865 lines
23 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef NEXTPNR_H
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#error Include "arch.h" via "nextpnr.h" only.
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#endif
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NEXTPNR_NAMESPACE_BEGIN
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/**** Everything in this section must be kept in sync with chipdb.py ****/
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template <typename T> struct RelPtr
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{
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int32_t offset;
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// void set(const T *ptr) {
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// offset = reinterpret_cast<const char*>(ptr) -
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// reinterpret_cast<const char*>(this);
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// }
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const T *get() const { return reinterpret_cast<const T *>(reinterpret_cast<const char *>(this) + offset); }
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const T &operator[](size_t index) const { return get()[index]; }
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const T &operator*() const { return *(get()); }
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const T *operator->() const { return get(); }
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};
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NPNR_PACKED_STRUCT(struct BelWirePOD {
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int32_t port;
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int32_t type;
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int32_t wire_index;
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});
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NPNR_PACKED_STRUCT(struct BelInfoPOD {
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RelPtr<char> name;
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int32_t type;
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int32_t num_bel_wires;
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RelPtr<BelWirePOD> bel_wires;
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int8_t x, y, z;
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int8_t padding_0;
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});
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NPNR_PACKED_STRUCT(struct BelPortPOD {
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int32_t bel_index;
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int32_t port;
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});
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NPNR_PACKED_STRUCT(struct PipInfoPOD {
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enum PipFlags : uint32_t
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{
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FLAG_NONE = 0,
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FLAG_ROUTETHRU = 1,
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FLAG_NOCARRY = 2
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};
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// RelPtr<char> name;
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int32_t src, dst;
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int32_t fast_delay;
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int32_t slow_delay;
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int8_t x, y;
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int16_t src_seg, dst_seg;
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int16_t switch_mask;
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int32_t switch_index;
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PipFlags flags;
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});
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NPNR_PACKED_STRUCT(struct WireSegmentPOD {
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int8_t x, y;
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int16_t index;
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});
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NPNR_PACKED_STRUCT(struct WireInfoPOD {
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enum WireType : int8_t
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{
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WIRE_TYPE_NONE = 0,
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WIRE_TYPE_GLB2LOCAL = 1,
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WIRE_TYPE_GLB_NETWK = 2,
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WIRE_TYPE_LOCAL = 3,
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WIRE_TYPE_LUTFF_IN = 4,
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WIRE_TYPE_LUTFF_IN_LUT = 5,
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WIRE_TYPE_LUTFF_LOUT = 6,
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WIRE_TYPE_LUTFF_OUT = 7,
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WIRE_TYPE_LUTFF_COUT = 8,
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WIRE_TYPE_LUTFF_GLOBAL = 9,
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WIRE_TYPE_CARRY_IN_MUX = 10,
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WIRE_TYPE_SP4_V = 11,
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WIRE_TYPE_SP4_H = 12,
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WIRE_TYPE_SP12_V = 13,
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WIRE_TYPE_SP12_H = 14
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};
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RelPtr<char> name;
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int32_t num_uphill, num_downhill;
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RelPtr<int32_t> pips_uphill, pips_downhill;
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int32_t num_bel_pins;
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RelPtr<BelPortPOD> bel_pins;
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int32_t num_segments;
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RelPtr<WireSegmentPOD> segments;
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int32_t fast_delay;
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int32_t slow_delay;
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int8_t x, y, z;
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WireType type;
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});
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NPNR_PACKED_STRUCT(struct PackagePinPOD {
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RelPtr<char> name;
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int32_t bel_index;
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});
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NPNR_PACKED_STRUCT(struct PackageInfoPOD {
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RelPtr<char> name;
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int32_t num_pins;
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RelPtr<PackagePinPOD> pins;
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});
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enum TileType : uint32_t
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{
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TILE_NONE = 0,
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TILE_LOGIC = 1,
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TILE_IO = 2,
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TILE_RAMB = 3,
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TILE_RAMT = 4,
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TILE_DSP0 = 5,
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TILE_DSP1 = 6,
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TILE_DSP2 = 7,
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TILE_DSP3 = 8,
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TILE_IPCON = 9
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};
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NPNR_PACKED_STRUCT(struct ConfigBitPOD { int8_t row, col; });
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NPNR_PACKED_STRUCT(struct ConfigEntryPOD {
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RelPtr<char> name;
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int32_t num_bits;
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RelPtr<ConfigBitPOD> bits;
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});
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NPNR_PACKED_STRUCT(struct TileInfoPOD {
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int8_t cols, rows;
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int16_t num_config_entries;
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RelPtr<ConfigEntryPOD> entries;
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});
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static const int max_switch_bits = 5;
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NPNR_PACKED_STRUCT(struct SwitchInfoPOD {
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int32_t num_bits;
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int32_t bel;
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int8_t x, y;
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ConfigBitPOD cbits[max_switch_bits];
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});
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NPNR_PACKED_STRUCT(struct IerenInfoPOD {
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int8_t iox, ioy, ioz;
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int8_t ierx, iery, ierz;
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});
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NPNR_PACKED_STRUCT(struct BitstreamInfoPOD {
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int32_t num_switches, num_ierens;
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RelPtr<TileInfoPOD> tiles_nonrouting;
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RelPtr<SwitchInfoPOD> switches;
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RelPtr<IerenInfoPOD> ierens;
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});
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NPNR_PACKED_STRUCT(struct BelConfigEntryPOD {
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RelPtr<char> entry_name;
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RelPtr<char> cbit_name;
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int8_t x, y;
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int16_t padding;
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});
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// Stores mapping between bel parameters and config bits,
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// for extra cells where this mapping is non-trivial
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NPNR_PACKED_STRUCT(struct BelConfigPOD {
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int32_t bel_index;
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int32_t num_entries;
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RelPtr<BelConfigEntryPOD> entries;
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});
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NPNR_PACKED_STRUCT(struct CellPathDelayPOD {
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int32_t from_port;
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int32_t to_port;
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int32_t fast_delay;
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int32_t slow_delay;
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});
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NPNR_PACKED_STRUCT(struct CellTimingPOD {
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int32_t type;
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int32_t num_paths;
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RelPtr<CellPathDelayPOD> path_delays;
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});
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NPNR_PACKED_STRUCT(struct ChipInfoPOD {
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int32_t width, height;
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int32_t num_bels, num_wires, num_pips;
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int32_t num_switches, num_belcfgs, num_packages;
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int32_t num_timing_cells;
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RelPtr<BelInfoPOD> bel_data;
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RelPtr<WireInfoPOD> wire_data;
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RelPtr<PipInfoPOD> pip_data;
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RelPtr<TileType> tile_grid;
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RelPtr<BitstreamInfoPOD> bits_info;
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RelPtr<BelConfigPOD> bel_config;
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RelPtr<PackageInfoPOD> packages_data;
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RelPtr<CellTimingPOD> cell_timing;
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RelPtr<RelPtr<char>> tile_wire_names;
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});
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#if defined(_MSC_VER)
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extern const char *chipdb_blob_384;
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extern const char *chipdb_blob_1k;
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extern const char *chipdb_blob_5k;
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extern const char *chipdb_blob_8k;
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#else
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extern const char chipdb_blob_384[];
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extern const char chipdb_blob_1k[];
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extern const char chipdb_blob_5k[];
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extern const char chipdb_blob_8k[];
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#endif
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/************************ End of chipdb section. ************************/
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struct BelIterator
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{
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int cursor;
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BelIterator operator++()
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{
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cursor++;
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return *this;
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}
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BelIterator operator++(int)
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{
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BelIterator prior(*this);
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cursor++;
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return prior;
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}
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bool operator!=(const BelIterator &other) const { return cursor != other.cursor; }
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bool operator==(const BelIterator &other) const { return cursor == other.cursor; }
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BelId operator*() const
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{
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BelId ret;
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ret.index = cursor;
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return ret;
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}
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};
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struct BelRange
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{
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BelIterator b, e;
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BelIterator begin() const { return b; }
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BelIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct BelPinIterator
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{
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const BelPortPOD *ptr = nullptr;
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void operator++() { ptr++; }
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bool operator!=(const BelPinIterator &other) const { return ptr != other.ptr; }
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BelPin operator*() const
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{
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BelPin ret;
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ret.bel.index = ptr->bel_index;
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ret.pin = ptr->port;
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return ret;
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}
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};
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struct BelPinRange
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{
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BelPinIterator b, e;
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BelPinIterator begin() const { return b; }
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BelPinIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct WireIterator
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{
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int cursor = -1;
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void operator++() { cursor++; }
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bool operator!=(const WireIterator &other) const { return cursor != other.cursor; }
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WireId operator*() const
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{
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WireId ret;
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ret.index = cursor;
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return ret;
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}
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};
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struct WireRange
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{
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WireIterator b, e;
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WireIterator begin() const { return b; }
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WireIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct AllPipIterator
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{
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int cursor = -1;
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void operator++() { cursor++; }
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bool operator!=(const AllPipIterator &other) const { return cursor != other.cursor; }
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PipId operator*() const
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{
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PipId ret;
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ret.index = cursor;
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return ret;
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}
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};
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struct AllPipRange
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{
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AllPipIterator b, e;
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AllPipIterator begin() const { return b; }
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AllPipIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct PipIterator
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{
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const int *cursor = nullptr;
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void operator++() { cursor++; }
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bool operator!=(const PipIterator &other) const { return cursor != other.cursor; }
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PipId operator*() const
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{
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PipId ret;
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ret.index = *cursor;
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return ret;
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}
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};
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struct PipRange
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{
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PipIterator b, e;
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PipIterator begin() const { return b; }
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PipIterator end() const { return e; }
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};
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struct ArchArgs
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{
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enum ArchArgsTypes
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{
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NONE,
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LP384,
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LP1K,
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LP8K,
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HX1K,
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HX8K,
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UP5K
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} type = NONE;
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std::string package;
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};
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struct Arch : BaseCtx
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{
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bool fast_part;
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const ChipInfoPOD *chip_info;
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const PackageInfoPOD *package_info;
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mutable std::unordered_map<IdString, int> bel_by_name;
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mutable std::unordered_map<IdString, int> wire_by_name;
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mutable std::unordered_map<IdString, int> pip_by_name;
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mutable std::unordered_map<Loc, int> bel_by_loc;
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std::vector<bool> bel_carry;
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std::vector<CellInfo *> bel_to_cell;
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std::vector<NetInfo *> wire_to_net;
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std::vector<NetInfo *> pip_to_net;
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std::vector<WireId> switches_locked;
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ArchArgs args;
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Arch(ArchArgs args);
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std::string getChipName() const;
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IdString archId() const { return id("ice40"); }
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ArchArgs archArgs() const { return args; }
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IdString archArgsToId(ArchArgs args) const;
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// -------------------------------------------------
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int getGridDimX() const { return 34; }
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int getGridDimY() const { return 34; }
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int getTileBelDimZ(int, int) const { return 8; }
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int getTilePipDimZ(int, int) const { return 1; }
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// -------------------------------------------------
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BelId getBelByName(IdString name) const;
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IdString getBelName(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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return id(chip_info->bel_data[bel.index].name.get());
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}
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uint32_t getBelChecksum(BelId bel) const { return bel.index; }
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void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength)
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{
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NPNR_ASSERT(bel != BelId());
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NPNR_ASSERT(bel_to_cell[bel.index] == nullptr);
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bel_to_cell[bel.index] = cell;
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bel_carry[bel.index] = (cell->type == id_ICESTORM_LC && cell->lcInfo.carryEnable);
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cell->bel = bel;
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cell->belStrength = strength;
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refreshUiBel(bel);
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}
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void unbindBel(BelId bel)
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{
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NPNR_ASSERT(bel != BelId());
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NPNR_ASSERT(bel_to_cell[bel.index] != nullptr);
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bel_to_cell[bel.index]->bel = BelId();
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bel_to_cell[bel.index]->belStrength = STRENGTH_NONE;
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bel_to_cell[bel.index] = nullptr;
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bel_carry[bel.index] = false;
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refreshUiBel(bel);
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}
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bool checkBelAvail(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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return bel_to_cell[bel.index] == nullptr;
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}
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CellInfo *getBoundBelCell(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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return bel_to_cell[bel.index];
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}
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CellInfo *getConflictingBelCell(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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return bel_to_cell[bel.index];
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}
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BelRange getBels() const
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{
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BelRange range;
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range.b.cursor = 0;
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range.e.cursor = chip_info->num_bels;
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return range;
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}
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Loc getBelLocation(BelId bel) const
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{
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Loc loc;
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loc.x = chip_info->bel_data[bel.index].x;
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loc.y = chip_info->bel_data[bel.index].y;
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loc.z = chip_info->bel_data[bel.index].z;
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return loc;
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}
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BelId getBelByLocation(Loc loc) const;
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BelRange getBelsByTile(int x, int y) const;
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bool getBelGlobalBuf(BelId bel) const { return chip_info->bel_data[bel.index].type == ID_SB_GB; }
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IdString getBelType(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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return IdString(chip_info->bel_data[bel.index].type);
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}
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std::vector<std::pair<IdString, std::string>> getBelAttrs(BelId bel) const;
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WireId getBelPinWire(BelId bel, IdString pin) const;
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PortType getBelPinType(BelId bel, IdString pin) const;
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std::vector<IdString> getBelPins(BelId bel) const;
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// -------------------------------------------------
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WireId getWireByName(IdString name) const;
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IdString getWireName(WireId wire) const
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{
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NPNR_ASSERT(wire != WireId());
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return id(chip_info->wire_data[wire.index].name.get());
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}
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IdString getWireType(WireId wire) const;
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std::vector<std::pair<IdString, std::string>> getWireAttrs(WireId wire) const;
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uint32_t getWireChecksum(WireId wire) const { return wire.index; }
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void bindWire(WireId wire, NetInfo *net, PlaceStrength strength)
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{
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NPNR_ASSERT(wire != WireId());
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NPNR_ASSERT(wire_to_net[wire.index] == nullptr);
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wire_to_net[wire.index] = net;
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net->wires[wire].pip = PipId();
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net->wires[wire].strength = strength;
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refreshUiWire(wire);
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}
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void unbindWire(WireId wire)
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{
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NPNR_ASSERT(wire != WireId());
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NPNR_ASSERT(wire_to_net[wire.index] != nullptr);
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auto &net_wires = wire_to_net[wire.index]->wires;
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auto it = net_wires.find(wire);
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NPNR_ASSERT(it != net_wires.end());
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auto pip = it->second.pip;
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if (pip != PipId()) {
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pip_to_net[pip.index] = nullptr;
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switches_locked[chip_info->pip_data[pip.index].switch_index] = WireId();
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}
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net_wires.erase(it);
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wire_to_net[wire.index] = nullptr;
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refreshUiWire(wire);
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|
}
|
|
|
|
bool checkWireAvail(WireId wire) const
|
|
{
|
|
NPNR_ASSERT(wire != WireId());
|
|
return wire_to_net[wire.index] == nullptr;
|
|
}
|
|
|
|
NetInfo *getBoundWireNet(WireId wire) const
|
|
{
|
|
NPNR_ASSERT(wire != WireId());
|
|
return wire_to_net[wire.index];
|
|
}
|
|
|
|
WireId getConflictingWireWire(WireId wire) const { return wire; }
|
|
|
|
NetInfo *getConflictingWireNet(WireId wire) const
|
|
{
|
|
NPNR_ASSERT(wire != WireId());
|
|
return wire_to_net[wire.index];
|
|
}
|
|
|
|
DelayInfo getWireDelay(WireId wire) const
|
|
{
|
|
DelayInfo delay;
|
|
NPNR_ASSERT(wire != WireId());
|
|
if (fast_part)
|
|
delay.delay = chip_info->wire_data[wire.index].fast_delay;
|
|
else
|
|
delay.delay = chip_info->wire_data[wire.index].slow_delay;
|
|
return delay;
|
|
}
|
|
|
|
BelPinRange getWireBelPins(WireId wire) const
|
|
{
|
|
BelPinRange range;
|
|
NPNR_ASSERT(wire != WireId());
|
|
range.b.ptr = chip_info->wire_data[wire.index].bel_pins.get();
|
|
range.e.ptr = range.b.ptr + chip_info->wire_data[wire.index].num_bel_pins;
|
|
return range;
|
|
}
|
|
|
|
WireRange getWires() const
|
|
{
|
|
WireRange range;
|
|
range.b.cursor = 0;
|
|
range.e.cursor = chip_info->num_wires;
|
|
return range;
|
|
}
|
|
|
|
// -------------------------------------------------
|
|
|
|
PipId getPipByName(IdString name) const;
|
|
|
|
void bindPip(PipId pip, NetInfo *net, PlaceStrength strength)
|
|
{
|
|
NPNR_ASSERT(pip != PipId());
|
|
NPNR_ASSERT(pip_to_net[pip.index] == nullptr);
|
|
NPNR_ASSERT(switches_locked[chip_info->pip_data[pip.index].switch_index] == WireId());
|
|
|
|
WireId dst;
|
|
dst.index = chip_info->pip_data[pip.index].dst;
|
|
NPNR_ASSERT(wire_to_net[dst.index] == nullptr);
|
|
|
|
pip_to_net[pip.index] = net;
|
|
switches_locked[chip_info->pip_data[pip.index].switch_index] = dst;
|
|
|
|
wire_to_net[dst.index] = net;
|
|
net->wires[dst].pip = pip;
|
|
net->wires[dst].strength = strength;
|
|
refreshUiPip(pip);
|
|
refreshUiWire(dst);
|
|
}
|
|
|
|
void unbindPip(PipId pip)
|
|
{
|
|
NPNR_ASSERT(pip != PipId());
|
|
NPNR_ASSERT(pip_to_net[pip.index] != nullptr);
|
|
NPNR_ASSERT(switches_locked[chip_info->pip_data[pip.index].switch_index] != WireId());
|
|
|
|
WireId dst;
|
|
dst.index = chip_info->pip_data[pip.index].dst;
|
|
NPNR_ASSERT(wire_to_net[dst.index] != nullptr);
|
|
wire_to_net[dst.index] = nullptr;
|
|
pip_to_net[pip.index]->wires.erase(dst);
|
|
|
|
pip_to_net[pip.index] = nullptr;
|
|
switches_locked[chip_info->pip_data[pip.index].switch_index] = WireId();
|
|
refreshUiPip(pip);
|
|
refreshUiWire(dst);
|
|
}
|
|
|
|
bool ice40_pip_hard_unavail(PipId pip) const
|
|
{
|
|
NPNR_ASSERT(pip != PipId());
|
|
auto &pi = chip_info->pip_data[pip.index];
|
|
auto &si = chip_info->bits_info->switches[pi.switch_index];
|
|
|
|
if (pi.flags & PipInfoPOD::FLAG_ROUTETHRU) {
|
|
NPNR_ASSERT(si.bel >= 0);
|
|
if (bel_to_cell[si.bel] != nullptr)
|
|
return true;
|
|
}
|
|
|
|
if (pi.flags & PipInfoPOD::FLAG_NOCARRY) {
|
|
NPNR_ASSERT(si.bel >= 0);
|
|
if (bel_carry[si.bel])
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
bool checkPipAvail(PipId pip) const
|
|
{
|
|
if (ice40_pip_hard_unavail(pip))
|
|
return false;
|
|
|
|
auto &pi = chip_info->pip_data[pip.index];
|
|
return switches_locked[pi.switch_index] == WireId();
|
|
}
|
|
|
|
NetInfo *getBoundPipNet(PipId pip) const
|
|
{
|
|
NPNR_ASSERT(pip != PipId());
|
|
return pip_to_net[pip.index];
|
|
}
|
|
|
|
WireId getConflictingPipWire(PipId pip) const
|
|
{
|
|
if (ice40_pip_hard_unavail(pip))
|
|
return WireId();
|
|
|
|
return switches_locked[chip_info->pip_data[pip.index].switch_index];
|
|
}
|
|
|
|
NetInfo *getConflictingPipNet(PipId pip) const
|
|
{
|
|
if (ice40_pip_hard_unavail(pip))
|
|
return nullptr;
|
|
|
|
WireId wire = switches_locked[chip_info->pip_data[pip.index].switch_index];
|
|
return wire == WireId() ? nullptr : wire_to_net[wire.index];
|
|
}
|
|
|
|
AllPipRange getPips() const
|
|
{
|
|
AllPipRange range;
|
|
range.b.cursor = 0;
|
|
range.e.cursor = chip_info->num_pips;
|
|
return range;
|
|
}
|
|
|
|
Loc getPipLocation(PipId pip) const
|
|
{
|
|
Loc loc;
|
|
loc.x = chip_info->pip_data[pip.index].x;
|
|
loc.y = chip_info->pip_data[pip.index].y;
|
|
loc.z = 0;
|
|
return loc;
|
|
}
|
|
|
|
IdString getPipName(PipId pip) const;
|
|
|
|
IdString getPipType(PipId pip) const;
|
|
std::vector<std::pair<IdString, std::string>> getPipAttrs(PipId pip) const;
|
|
|
|
uint32_t getPipChecksum(PipId pip) const { return pip.index; }
|
|
|
|
WireId getPipSrcWire(PipId pip) const
|
|
{
|
|
WireId wire;
|
|
NPNR_ASSERT(pip != PipId());
|
|
wire.index = chip_info->pip_data[pip.index].src;
|
|
return wire;
|
|
}
|
|
|
|
WireId getPipDstWire(PipId pip) const
|
|
{
|
|
WireId wire;
|
|
NPNR_ASSERT(pip != PipId());
|
|
wire.index = chip_info->pip_data[pip.index].dst;
|
|
return wire;
|
|
}
|
|
|
|
DelayInfo getPipDelay(PipId pip) const
|
|
{
|
|
DelayInfo delay;
|
|
NPNR_ASSERT(pip != PipId());
|
|
if (fast_part)
|
|
delay.delay = chip_info->pip_data[pip.index].fast_delay;
|
|
else
|
|
delay.delay = chip_info->pip_data[pip.index].slow_delay;
|
|
return delay;
|
|
}
|
|
|
|
PipRange getPipsDownhill(WireId wire) const
|
|
{
|
|
PipRange range;
|
|
NPNR_ASSERT(wire != WireId());
|
|
range.b.cursor = chip_info->wire_data[wire.index].pips_downhill.get();
|
|
range.e.cursor = range.b.cursor + chip_info->wire_data[wire.index].num_downhill;
|
|
return range;
|
|
}
|
|
|
|
PipRange getPipsUphill(WireId wire) const
|
|
{
|
|
PipRange range;
|
|
NPNR_ASSERT(wire != WireId());
|
|
range.b.cursor = chip_info->wire_data[wire.index].pips_uphill.get();
|
|
range.e.cursor = range.b.cursor + chip_info->wire_data[wire.index].num_uphill;
|
|
return range;
|
|
}
|
|
|
|
PipRange getWireAliases(WireId wire) const
|
|
{
|
|
PipRange range;
|
|
NPNR_ASSERT(wire != WireId());
|
|
range.b.cursor = nullptr;
|
|
range.e.cursor = nullptr;
|
|
return range;
|
|
}
|
|
|
|
BelId getPackagePinBel(const std::string &pin) const;
|
|
std::string getBelPackagePin(BelId bel) const;
|
|
|
|
// -------------------------------------------------
|
|
|
|
GroupId getGroupByName(IdString name) const;
|
|
IdString getGroupName(GroupId group) const;
|
|
std::vector<GroupId> getGroups() const;
|
|
std::vector<BelId> getGroupBels(GroupId group) const;
|
|
std::vector<WireId> getGroupWires(GroupId group) const;
|
|
std::vector<PipId> getGroupPips(GroupId group) const;
|
|
std::vector<GroupId> getGroupGroups(GroupId group) const;
|
|
|
|
// -------------------------------------------------
|
|
|
|
delay_t estimateDelay(WireId src, WireId dst) const;
|
|
delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
|
|
delay_t getDelayEpsilon() const { return 20; }
|
|
delay_t getRipupDelayPenalty() const { return 200; }
|
|
float getDelayNS(delay_t v) const { return v * 0.001; }
|
|
uint32_t getDelayChecksum(delay_t v) const { return v; }
|
|
bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const;
|
|
|
|
// -------------------------------------------------
|
|
|
|
bool pack();
|
|
bool place();
|
|
bool route();
|
|
|
|
// -------------------------------------------------
|
|
|
|
std::vector<GraphicElement> getDecalGraphics(DecalId decal) const;
|
|
|
|
DecalXY getBelDecal(BelId bel) const;
|
|
DecalXY getWireDecal(WireId wire) const;
|
|
DecalXY getPipDecal(PipId pip) const;
|
|
DecalXY getGroupDecal(GroupId group) const;
|
|
|
|
// -------------------------------------------------
|
|
|
|
// Get the delay through a cell from one port to another, returning false
|
|
// if no path exists
|
|
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
|
|
// Get the port class, also setting clockDomain if applicable
|
|
TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockDomain) const;
|
|
// Return true if a port is a net
|
|
bool isGlobalNet(const NetInfo *net) const;
|
|
|
|
// -------------------------------------------------
|
|
|
|
// Perform placement validity checks, returning false on failure (all
|
|
// implemented in arch_place.cc)
|
|
|
|
// Whether or not a given cell can be placed at a given Bel
|
|
// This is not intended for Bel type checks, but finer-grained constraints
|
|
// such as conflicting set/reset signals, etc
|
|
bool isValidBelForCell(CellInfo *cell, BelId bel) const;
|
|
|
|
// Return true whether all Bels at a given location are valid
|
|
bool isBelLocationValid(BelId bel) const;
|
|
|
|
// Helper function for above
|
|
bool logicCellsCompatible(const CellInfo **it, const size_t size) const;
|
|
|
|
// -------------------------------------------------
|
|
// Assign architecure-specific arguments to nets and cells, which must be
|
|
// called between packing or further
|
|
// netlist modifications, and validity checks
|
|
void assignArchInfo();
|
|
void assignCellInfo(CellInfo *cell);
|
|
|
|
// -------------------------------------------------
|
|
BelPin getIOBSharingPLLPin(BelId pll, IdString pll_pin) const
|
|
{
|
|
auto wire = getBelPinWire(pll, pll_pin);
|
|
for (auto src_bel : getWireBelPins(wire)) {
|
|
if (getBelType(src_bel.bel) == id_SB_IO && src_bel.pin == id_D_IN_0) {
|
|
return src_bel;
|
|
}
|
|
}
|
|
NPNR_ASSERT_FALSE("Expected PLL pin to share an output with an SB_IO D_IN_{0,1}");
|
|
}
|
|
};
|
|
|
|
void ice40DelayFuzzerMain(Context *ctx);
|
|
|
|
NEXTPNR_NAMESPACE_END
|