7922b3bfc4
This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
55 lines
1.7 KiB
C++
55 lines
1.7 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef NEXTPNR_H
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#error Include "archdefs.h" via "nextpnr.h" only.
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#endif
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NEXTPNR_NAMESPACE_BEGIN
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typedef float delay_t;
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typedef IdStringList BelId;
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typedef IdStringList WireId;
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typedef IdStringList PipId;
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typedef IdStringList GroupId;
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typedef IdStringList DecalId;
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typedef IdString BelBucketId;
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struct ArchNetInfo
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{
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};
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struct NetInfo;
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struct ArchCellInfo
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{
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// Custom grouping set via "PACK_GROUP" attribute. All cells with the same group
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// value may share a tile (-1 = don't care, default if not set)
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int user_group;
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// Is a slice type primitive
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bool is_slice;
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// Only packing rule for slice type primitives is a single clock per tile
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const NetInfo *slice_clk;
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// Cell to bel pin mapping
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std::unordered_map<IdString, std::vector<IdString>> bel_pins;
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};
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NEXTPNR_NAMESPACE_END
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