0994e11b73
Information about what function (main or auxiliary) the cell performs in these primitives is transmitted through the tile's extra data. And this also allows us to remove the calculation of the coordinates of the auxiliary cell on the go. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
401 lines
13 KiB
C++
401 lines
13 KiB
C++
#include <regex>
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#include "himbaechel_api.h"
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#include "himbaechel_helpers.h"
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#include "log.h"
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#include "nextpnr.h"
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#define GEN_INIT_CONSTIDS
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#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
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#include "himbaechel_constids.h"
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#include "cst.h"
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#include "globals.h"
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#include "gowin.h"
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#include "gowin_utils.h"
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#include "pack.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace {
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struct GowinImpl : HimbaechelAPI
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{
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~GowinImpl(){};
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void init_constids(Arch *arch) override { init_uarch_constids(arch); }
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void init(Context *ctx) override;
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void pack() override;
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void prePlace() override;
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void postPlace() override;
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void preRoute() override;
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void postRoute() override;
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bool isBelLocationValid(BelId bel, bool explain_invalid) const override;
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// Bel bucket functions
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IdString getBelBucketForCellType(IdString cell_type) const override;
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bool isValidBelForCellType(IdString cell_type, BelId bel) const override;
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private:
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HimbaechelHelpers h;
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GowinUtils gwu;
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IdString chip;
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IdString partno;
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std::set<BelId> inactive_bels;
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// Validity checking
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struct GowinCellInfo
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{
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const NetInfo *lut_f = nullptr;
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const NetInfo *ff_d = nullptr, *ff_ce = nullptr, *ff_clk = nullptr, *ff_lsr = nullptr;
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const NetInfo *alu_sum = nullptr;
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};
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std::vector<GowinCellInfo> fast_cell_info;
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void assign_cell_info();
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// bel placement validation
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bool slice_valid(int x, int y, int z) const;
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};
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struct GowinArch : HimbaechelArch
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{
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GowinArch() : HimbaechelArch("gowin"){};
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std::unique_ptr<HimbaechelAPI> create(const dict<std::string, std::string> &args)
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{
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return std::make_unique<GowinImpl>();
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}
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} gowinrArch;
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void GowinImpl::init(Context *ctx)
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{
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h.init(ctx);
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HimbaechelAPI::init(ctx);
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gwu.init(ctx);
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const ArchArgs &args = ctx->getArchArgs();
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// These fields go in the header of the output JSON file and can help
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// gowin_pack support different architectures
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ctx->settings[ctx->id("packer.arch")] = std::string("himbaechel/gowin");
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ctx->settings[ctx->id("packer.chipdb")] = args.chipdb;
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if (!args.options.count("partno")) {
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log_error("Partnumber (like --vopt partno=GW1NR-LV9QN88PC6/I5) must be specified.\n");
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}
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// GW1N-9C.xxx -> GW1N-9C
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std::string chipdb = args.chipdb;
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auto dot_pos = chipdb.find(".");
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if (dot_pos != std::string::npos) {
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chipdb.resize(dot_pos);
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}
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chip = ctx->id(chipdb);
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std::string pn = args.options.at("partno");
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partno = ctx->id(pn);
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ctx->settings[ctx->id("packer.partno")] = pn;
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// package and speed class
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std::regex speedre = std::regex("(.*)(C[0-9]/I[0-9])$");
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std::smatch match;
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IdString spd;
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IdString package_idx;
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if (std::regex_match(pn, match, speedre)) {
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package_idx = ctx->id(match[1]);
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spd = ctx->id(match[2]);
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} else {
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if (pn.length() > 2 && pn.compare(pn.length() - 2, 2, "ES")) {
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package_idx = ctx->id(pn.substr(pn.length() - 2));
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spd = ctx->id("ES");
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}
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}
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if (ctx->debug) {
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log_info("packages:%ld\n", ctx->chip_info->packages.ssize());
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}
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for (int i = 0; i < ctx->chip_info->packages.ssize(); ++i) {
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if (IdString(ctx->chip_info->packages[i].name) == package_idx) {
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if (ctx->debug) {
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log_info("i:%d %s\n", i, package_idx.c_str(ctx));
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}
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ctx->package_info = &ctx->chip_info->packages[i];
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break;
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}
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}
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if (ctx->package_info == nullptr) {
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log_error("No package for partnumber %s\n", partno.c_str(ctx));
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}
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// constraints
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if (args.options.count("cst")) {
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ctx->settings[ctx->id("cst.filename")] = args.options.at("cst");
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}
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}
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void GowinImpl::pack()
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{
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if (ctx->settings.count(ctx->id("cst.filename"))) {
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std::string filename = ctx->settings[ctx->id("cst.filename")].as_string();
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std::ifstream in(filename);
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if (!in) {
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log_error("failed to open CST file '%s'\n", filename.c_str());
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}
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if (!gowin_apply_constraints(ctx, in)) {
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log_error("failed to parse CST file '%s'\n", filename.c_str());
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}
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}
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gowin_pack(ctx);
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}
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void GowinImpl::prePlace() { assign_cell_info(); }
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void GowinImpl::postPlace()
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{
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if (ctx->debug) {
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log_info("================== Final Placement ===================\n");
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for (auto &cell : ctx->cells) {
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auto ci = cell.second.get();
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if (ci->bel != BelId()) {
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log_info("%s: %s\n", ctx->nameOfBel(ci->bel), ctx->nameOf(ci));
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} else {
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log_info("unknown: %s\n", ctx->nameOf(ci));
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}
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}
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log_break();
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}
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}
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void GowinImpl::preRoute() { gowin_route_globals(ctx); }
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void GowinImpl::postRoute()
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{
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std::set<IdString> visited_hclk_users;
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for (auto &cell : ctx->cells) {
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auto ci = cell.second.get();
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if (ci->type == id_IOLOGIC || (is_iologic(ci) && !ci->type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC))) {
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if (visited_hclk_users.find(ci->name) == visited_hclk_users.end()) {
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// mark FCLK<-HCLK connections
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const NetInfo *h_net = ci->getPort(id_FCLK);
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if (h_net) {
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for (auto &user : h_net->users) {
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if (user.port != id_FCLK) {
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continue;
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}
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user.cell->setAttr(id_IOLOGIC_FCLK, Property("UNKNOWN"));
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visited_hclk_users.insert(user.cell->name);
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// XXX Based on the implementation, perhaps a function
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// is needed to get Pip from a Wire
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PipId up_pip = h_net->wires.at(ctx->getNetinfoSinkWire(h_net, user, 0)).pip;
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IdString up_wire_name = ctx->getWireName(ctx->getPipSrcWire(up_pip))[1];
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if (up_wire_name.in(id_HCLK_OUT0, id_HCLK_OUT1, id_HCLK_OUT2, id_HCLK_OUT3)) {
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user.cell->setAttr(id_IOLOGIC_FCLK, Property(up_wire_name.str(ctx)));
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if (ctx->debug) {
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log_info("set IOLOGIC_FCLK to %s\n", up_wire_name.c_str(ctx));
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}
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}
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if (ctx->debug) {
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log_info("HCLK user cell:%s, port:%s, wire:%s, pip:%s, up wire:%s\n",
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ctx->nameOf(user.cell), user.port.c_str(ctx),
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ctx->nameOfWire(ctx->getNetinfoSinkWire(h_net, user, 0)), ctx->nameOfPip(up_pip),
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ctx->nameOfWire(ctx->getPipSrcWire(up_pip)));
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}
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}
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}
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}
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}
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}
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}
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bool GowinImpl::isBelLocationValid(BelId bel, bool explain_invalid) const
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{
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Loc l = ctx->getBelLocation(bel);
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if (!ctx->getBoundBelCell(bel)) {
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return true;
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}
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IdString bel_type = ctx->getBelType(bel);
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switch (bel_type.hash()) {
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case ID_LUT4: /* fall-through */
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case ID_DFF:
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return slice_valid(l.x, l.y, l.z / 2);
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case ID_ALU:
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return slice_valid(l.x, l.y, l.z - BelZ::ALU0_Z);
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case ID_RAM16SDP4:
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// only slices 4 and 5 are critical for RAM
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return slice_valid(l.x, l.y, l.z - BelZ::RAMW_Z + 5) && slice_valid(l.x, l.y, l.z - BelZ::RAMW_Z + 4);
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}
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return true;
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}
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// Bel bucket functions
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IdString GowinImpl::getBelBucketForCellType(IdString cell_type) const
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{
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if (cell_type.in(id_IBUF, id_OBUF)) {
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return id_IOB;
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}
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if (type_is_lut(cell_type)) {
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return id_LUT4;
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}
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if (type_is_dff(cell_type)) {
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return id_DFF;
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}
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if (type_is_ssram(cell_type)) {
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return id_RAM16SDP4;
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}
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if (type_is_iologic(cell_type)) {
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return id_IOLOGIC;
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}
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if (cell_type == id_GOWIN_GND) {
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return id_GND;
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}
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if (cell_type == id_GOWIN_VCC) {
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return id_VCC;
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}
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return cell_type;
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}
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bool GowinImpl::isValidBelForCellType(IdString cell_type, BelId bel) const
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{
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IdString bel_type = ctx->getBelType(bel);
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if (bel_type == id_IOB) {
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return cell_type.in(id_IBUF, id_OBUF);
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}
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if (bel_type == id_LUT4) {
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return type_is_lut(cell_type);
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}
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if (bel_type == id_DFF) {
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return type_is_dff(cell_type);
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}
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if (bel_type == id_RAM16SDP4) {
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return type_is_ssram(cell_type);
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}
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if (bel_type == id_IOLOGIC) {
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return type_is_iologic(cell_type);
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}
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if (bel_type == id_GND) {
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return cell_type == id_GOWIN_GND;
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}
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if (bel_type == id_VCC) {
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return cell_type == id_GOWIN_VCC;
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}
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return (bel_type == cell_type);
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}
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void GowinImpl::assign_cell_info()
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{
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fast_cell_info.resize(ctx->cells.size());
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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auto &fc = fast_cell_info.at(ci->flat_index);
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if (is_lut(ci)) {
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fc.lut_f = ci->getPort(id_F);
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continue;
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}
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if (is_dff(ci)) {
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fc.ff_d = ci->getPort(id_D);
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fc.ff_clk = ci->getPort(id_CLK);
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fc.ff_ce = ci->getPort(id_CE);
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for (IdString port : {id_SET, id_RESET, id_PRESET, id_CLEAR}) {
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fc.ff_lsr = ci->getPort(port);
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if (fc.ff_lsr != nullptr) {
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break;
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}
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}
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continue;
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}
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if (is_alu(ci)) {
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fc.alu_sum = ci->getPort(id_SUM);
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continue;
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}
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}
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}
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// placement validation
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bool GowinImpl::slice_valid(int x, int y, int z) const
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{
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const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
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const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
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const CellInfo *alu = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z + BelZ::ALU0_Z)));
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const CellInfo *ramw =
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(z == 4 || z == 5) ? ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, BelZ::RAMW_Z))) : nullptr;
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if (alu && lut) {
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return false;
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}
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if (ramw) {
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if (alu || ff || lut) {
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return false;
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}
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return true;
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}
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// check for ALU/LUT in the adjacent cell
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int adj_lut_z = (1 - (z & 1) * 2 + z) * 2;
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int adj_alu_z = adj_lut_z / 2 + BelZ::ALU0_Z;
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const CellInfo *adj_lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_lut_z)));
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const CellInfo *adj_ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_lut_z + 1)));
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const CellInfo *adj_alu = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_alu_z)));
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if ((alu && (adj_lut || (adj_ff && !adj_alu))) || ((lut || (ff && !alu)) && adj_alu)) {
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return false;
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}
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// if there is DFF it must be connected to this LUT or ALU
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if (ff) {
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const auto &ff_data = fast_cell_info.at(ff->flat_index);
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if (lut) {
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const auto &lut_data = fast_cell_info.at(lut->flat_index);
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if (ff_data.ff_d != lut_data.lut_f) {
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return false;
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}
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}
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if (alu) {
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const auto &alu_data = fast_cell_info.at(alu->flat_index);
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if (ff_data.ff_d != alu_data.alu_sum) {
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return false;
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}
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}
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if (adj_ff) {
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// DFFs must be same type or compatible
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if (ff->type != adj_ff->type && ((ff->type.in(id_DFFS) && !adj_ff->type.in(id_DFFR)) ||
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(ff->type.in(id_DFFR) && !adj_ff->type.in(id_DFFS)) ||
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(ff->type.in(id_DFFSE) && !adj_ff->type.in(id_DFFRE)) ||
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(ff->type.in(id_DFFRE) && !adj_ff->type.in(id_DFFSE)) ||
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(ff->type.in(id_DFFP) && !adj_ff->type.in(id_DFFC)) ||
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(ff->type.in(id_DFFC) && !adj_ff->type.in(id_DFFP)) ||
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(ff->type.in(id_DFFPE) && !adj_ff->type.in(id_DFFCE)) ||
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(ff->type.in(id_DFFCE) && !adj_ff->type.in(id_DFFPE)) ||
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(ff->type.in(id_DFFNS) && !adj_ff->type.in(id_DFFNR)) ||
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(ff->type.in(id_DFFNR) && !adj_ff->type.in(id_DFFNS)) ||
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(ff->type.in(id_DFFNSE) && !adj_ff->type.in(id_DFFNRE)) ||
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(ff->type.in(id_DFFNRE) && !adj_ff->type.in(id_DFFNSE)) ||
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(ff->type.in(id_DFFNP) && !adj_ff->type.in(id_DFFNC)) ||
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(ff->type.in(id_DFFNC) && !adj_ff->type.in(id_DFFNP)) ||
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(ff->type.in(id_DFFNPE) && !adj_ff->type.in(id_DFFNCE)) ||
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(ff->type.in(id_DFFNCE) && !adj_ff->type.in(id_DFFNPE)))) {
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return false;
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}
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// CE, LSR and CLK must match
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const auto &adj_ff_data = fast_cell_info.at(adj_ff->flat_index);
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if (adj_ff_data.ff_lsr != ff_data.ff_lsr) {
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return false;
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}
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if (adj_ff_data.ff_clk != ff_data.ff_clk) {
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return false;
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}
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if (adj_ff_data.ff_ce != ff_data.ff_ce) {
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return false;
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}
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}
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}
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return true;
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}
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} // namespace
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NEXTPNR_NAMESPACE_END
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