252 lines
11 KiB
C++
252 lines
11 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021 Lofty <dan.ravensloft@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "nextpnr.h"
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NEXTPNR_NAMESPACE_BEGIN
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TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const
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{
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clockInfoCount = 0;
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if (cell->type.in(id_MISTRAL_NOT, id_MISTRAL_BUF, id_MISTRAL_ALUT2, id_MISTRAL_ALUT3, id_MISTRAL_ALUT4, id_MISTRAL_ALUT5, id_MISTRAL_ALUT6)) {
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if (port.in(id_A, id_B, id_C, id_D, id_E, id_F))
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return TMG_COMB_INPUT;
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if (port == id_Q)
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return TMG_COMB_OUTPUT;
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} else if (cell->type == id_MISTRAL_ALUT_ARITH) {
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if (port.in(id_A, id_B, id_C, id_D0, id_D1, id_CI))
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return TMG_COMB_INPUT;
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if (port.in(id_SO, id_CO))
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return TMG_COMB_OUTPUT;
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} else if (cell->type == id_MISTRAL_FF) {
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if (port == id_CLK) {
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return TMG_CLOCK_INPUT;
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}
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// ACLR is considered synchronous for timing purposes.
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else if (port.in(id_DATAIN, id_ACLR, id_ENA, id_SCLR, id_SLOAD, id_SDATA)) {
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clockInfoCount = 1;
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return TMG_REGISTER_INPUT;
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} else if (port == id_Q) {
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clockInfoCount = 1;
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return TMG_REGISTER_OUTPUT;
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}
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} else if (cell->type == id_MISTRAL_MLAB) {
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if (port == id_CLK1) {
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return TMG_CLOCK_INPUT;
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} else if (port.in(id_A1DATA, id_A1EN) || port.str(this).find("A1ADDR") == 0) {
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clockInfoCount = 1;
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return TMG_REGISTER_INPUT;
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} else if (port.str(this).find("B1ADDR") == 0) {
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return TMG_COMB_INPUT;
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} else if (port.in(id_B1DATA)) {
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return TMG_COMB_OUTPUT;
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}
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}
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return TMG_IGNORE;
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}
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TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const
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{
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TimingClockingInfo timing{};
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if (cell->type == id_MISTRAL_FF) {
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timing.clock_port = id_CLK;
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timing.edge = RISING_EDGE;
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// ACLR is considered synchronous for timing purposes.
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if (port.in(id_DATAIN, id_ACLR, id_ENA, id_SCLR, id_SLOAD, id_SDATA)) {
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timing.setup = DelayPair{-196, -196};
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timing.hold = DelayPair{270, 270};
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timing.clockToQ = DelayQuad{};
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} else if (port == id_Q) {
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timing.setup = DelayPair{};
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timing.hold = DelayPair{};
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timing.clockToQ = DelayQuad{731};
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}
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return timing;
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} else if (cell->type == id_MISTRAL_MLAB) {
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timing.clock_port = id_CLK1;
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timing.edge = RISING_EDGE;
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if (port.in(id_A1DATA, id_A1EN) || port.str(this).find("A1ADDR") == 0) {
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timing.setup = DelayPair{86, 86};
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timing.hold = DelayPair{42, 42};
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timing.clockToQ = DelayQuad{};
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}
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return timing;
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}
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NPNR_ASSERT_FALSE("unreachable");
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}
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bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const
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{
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// Based on 1.1V 100C timing corner of sx120f, using delays from LUT input to DFF input.
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// I have many regrets about naming my cell ports how I did...
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// TODO list:
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// - MLABs-as-LABs have different timings to LABs
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// - speed grades
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if (cell->type.in(id_MISTRAL_NOT, id_MISTRAL_BUF, id_MISTRAL_ALUT2, id_MISTRAL_ALUT3, id_MISTRAL_ALUT4, id_MISTRAL_ALUT5, id_MISTRAL_ALUT6)) {
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if (toPort == id_Q) {
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if (cell->type == id_MISTRAL_ALUT6 && fromPort == id_A) {
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delay = DelayQuad{/* RF */ 592, /* RR */ 605, /* FF */ 567, /* FR */ 573};
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return true;
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} else if ((cell->type == id_MISTRAL_ALUT5 && fromPort == id_A) ||
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(cell->type == id_MISTRAL_ALUT6 && fromPort == id_B)) {
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delay = DelayQuad{/* RF */ 580, /* RR */ 583, /* FF */ 560, /* FR */ 574};
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return true;
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} else if ((cell->type == id_MISTRAL_ALUT4 && fromPort == id_A) ||
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(cell->type == id_MISTRAL_ALUT5 && fromPort == id_B) ||
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(cell->type == id_MISTRAL_ALUT6 && fromPort == id_C)) {
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delay = DelayQuad{/* RR */ 429, /* RF */ 496, /* FR */ 440, /* FF */ 510};
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return true;
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} else if ((cell->type == id_MISTRAL_ALUT3 && fromPort == id_A) ||
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(cell->type == id_MISTRAL_ALUT4 && fromPort == id_B) ||
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(cell->type == id_MISTRAL_ALUT5 && fromPort == id_C) ||
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(cell->type == id_MISTRAL_ALUT6 && fromPort == id_D)) {
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delay = DelayQuad{/* RR */ 432, /* RF */ 499, /* FR */ 444, /* FF */ 512};
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return true;
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} else if ((cell->type == id_MISTRAL_ALUT2 && fromPort == id_A) ||
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(cell->type == id_MISTRAL_ALUT3 && fromPort == id_B) ||
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(cell->type == id_MISTRAL_ALUT4 && fromPort == id_C) ||
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(cell->type == id_MISTRAL_ALUT5 && fromPort == id_D) ||
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(cell->type == id_MISTRAL_ALUT6 && fromPort == id_E)) {
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delay = DelayQuad{/* RR */ 263, /* RF */ 354, /* FF */ 362, /* FR */ 400};
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return true;
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} else if ((cell->type.in(id_MISTRAL_NOT, id_MISTRAL_BUF) && fromPort == id_A) ||
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(cell->type == id_MISTRAL_ALUT2 && fromPort == id_B) ||
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(cell->type == id_MISTRAL_ALUT3 && fromPort == id_C) ||
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(cell->type == id_MISTRAL_ALUT4 && fromPort == id_D) ||
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(cell->type == id_MISTRAL_ALUT5 && fromPort == id_E) ||
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(cell->type == id_MISTRAL_ALUT6 && fromPort == id_F)) {
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delay = DelayQuad{/* RR */ 90, /* RF */ 96, /* FF */ 83, /* FR */ 97};
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return true;
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}
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}
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} else if (cell->type == id_MISTRAL_ALUT_ARITH) {
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if (toPort == id_CO) {
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if (fromPort == id_A) {
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delay = DelayQuad{/* RF */ 1005, /* RR */ 1082, /* FF */ 971, /* FR */ 1048};
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return true;
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} else if (fromPort == id_B) {
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delay = DelayQuad{/* RF */ 986, /* RR */ 1062, /* FF */ 976, /* FR */ 1052};
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return true;
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} else if (fromPort == id_C) {
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delay = DelayQuad{/* RF */ 736, /* RR */ 813, /* FF */ 775, /* FR */ 800};
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return true;
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} else if (fromPort == id_D0) {
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delay = DelayQuad{/* RF */ 822, /* RR */ 866, /* FF */ 837, /* FR */ 849};
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return true;
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} else if (fromPort == id_D1) {
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delay = DelayQuad{/* RF */ 1122, /* RR */ 1198, /* FF */ 1128, /* FR */ 1197};
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return true;
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} else if (fromPort == id_CI) {
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// Divided by 2 to account for delay being across ALM rather than across ALUT.
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// Maybe this should be a routing delay.
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delay = DelayQuad{/* RR */ 63 / 2, /* RR */ 71 / 2, /* FF */ 63 / 2, /* FR */ 71 / 2};
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return true;
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}
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} else if (toPort == id_SO) {
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if (fromPort == id_A) {
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delay = DelayQuad{/* RF */ 1300, /* RR */ 1342, /* FF */ 1266, /* FR */ 1308};
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return true;
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} else if (fromPort == id_B) {
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delay = DelayQuad{/* RF */ 1280, /* RR */ 1323, /* FF */ 1270, /* FR */ 1313};
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return true;
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} else if (fromPort == id_C) {
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delay = DelayQuad{/* RF */ 866, /* RR */ 892, /* FF */ 908, /* FR */ 927};
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return true;
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} else if (fromPort == id_D0) {
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delay = DelayQuad{/* RR */ 779, /* RF */ 887, /* FR */ 761, /* FF */ 883};
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return true;
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} else if (fromPort == id_D1) {
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delay = DelayQuad{/* RR */ 700, /* RF */ 785, /* FR */ 696, /* FF */ 782};
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return true;
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} else if (fromPort == id_CI) {
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delay = DelayQuad{/* RR */ 350, /* RF */ 352, /* FF */ 361, /* FR */ 368};
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return true;
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}
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}
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} else if (cell->type == id_MISTRAL_MLAB) {
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if (toPort == id_B1DATA) {
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if (fromPort.str(this) == "B1ADDR[0]") {
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delay = DelayQuad{/* RF */ 473, /* RR */ 487, /* FR */ 452, /* FF */ 476};
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return true;
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} else if (fromPort.str(this) == "B1ADDR[1]") {
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delay = DelayQuad{/* RF */ 472, /* RR */ 475, /* FR */ 444, /* FF */ 460};
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return true;
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} else if (fromPort.str(this) == "B1ADDR[2]") {
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delay = DelayQuad{/* RF */ 343, /* RR */ 347, /* FR */ 358, /* FF */ 382};
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return true;
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} else if (fromPort.str(this) == "B1ADDR[3]") {
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delay = DelayQuad{/* RF */ 263, /* RR */ 268, /* FF */ 256, /* FR */ 284};
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return true;
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} else if (fromPort.str(this) == "B1ADDR[4]") {
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delay = DelayQuad{/* RF */ 89, /* RR */ 96, /* FF */ 73, /* FR */ 93};
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return true;
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}
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}
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}
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return false;
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}
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DelayQuad Arch::getPipDelay(PipId pip) const
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{
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WireId src = getPipSrcWire(pip), dst = getPipDstWire(pip);
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if ((src.is_nextpnr_created() && dst.is_nextpnr_created()) || dst.is_nextpnr_created())
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return DelayQuad{20};
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// This is guesswork based on average of (interconnect delay / number of pips)
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auto dst_type = CycloneV::rn2t(dst.node);
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switch (dst_type) {
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case CycloneV::rnode_type_t::H14: return DelayQuad{254};
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case CycloneV::rnode_type_t::H3: return DelayQuad{214};
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case CycloneV::rnode_type_t::H6: return DelayQuad{298};
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case CycloneV::rnode_type_t::V2: return DelayQuad{210};
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case CycloneV::rnode_type_t::V4: return DelayQuad{262};
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case CycloneV::rnode_type_t::DCMUX: return DelayQuad{0};
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case CycloneV::rnode_type_t::GIN: return DelayQuad{83}; // need to check with Sarayan
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case CycloneV::rnode_type_t::GOUT: return DelayQuad{123};
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case CycloneV::rnode_type_t::TCLK: return DelayQuad{46};
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}
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return DelayQuad{308};
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}
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delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
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{
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if (net_info->driver.cell == nullptr || net_info->driver.cell->bel == BelId())
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return 100;
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if (sink.cell->bel == BelId())
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return 100;
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Loc src_loc = getBelLocation(net_info->driver.cell->bel);
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Loc dst_loc = getBelLocation(sink.cell->bel);
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return std::abs(dst_loc.y - src_loc.y) * 100 + std::abs(dst_loc.x - src_loc.x) * 100 + 100;
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}
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delay_t Arch::estimateDelay(WireId src, WireId dst) const
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{
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int x0 = CycloneV::rn2x(src.node);
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int y0 = CycloneV::rn2y(src.node);
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int x1 = CycloneV::rn2x(dst.node);
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int y1 = CycloneV::rn2y(dst.node);
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return 300 * std::abs(y1 - y0) + 300 * std::abs(x1 - x0) + 300;
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}
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NEXTPNR_NAMESPACE_END
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