640 lines
19 KiB
Rust
640 lines
19 KiB
Rust
use std::{
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collections::{BinaryHeap, HashMap, HashSet},
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time::Instant,
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};
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use colored::Colorize;
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use indicatif::{MultiProgress, ProgressBar, ProgressStyle};
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use itertools::Itertools;
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use crate::{
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npnr::{self, IdString, NetIndex, PipId, WireId},
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partition,
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};
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#[derive(Clone, Hash, PartialEq, Eq)]
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pub struct Arc {
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source_wire: WireId,
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sink_wire: WireId,
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net: NetIndex,
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name: IdString,
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}
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impl Arc {
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pub fn new(
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source_wire: npnr::WireId,
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sink_wire: npnr::WireId,
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net: NetIndex,
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name: IdString,
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) -> Self {
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Self {
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source_wire,
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sink_wire,
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net,
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name,
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}
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}
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pub fn split(&self, ctx: &npnr::Context, pip: npnr::PipId) -> (Self, Self) {
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let pip_src = ctx.pip_src_wire(pip);
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let pip_dst = ctx.pip_dst_wire(pip);
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(
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Self {
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source_wire: self.source_wire,
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sink_wire: pip_src,
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net: self.net,
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name: self.name,
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},
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Self {
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source_wire: pip_dst,
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sink_wire: self.sink_wire,
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net: self.net,
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name: self.name,
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},
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)
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}
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pub fn source_wire(&self) -> npnr::WireId {
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self.source_wire
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}
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pub fn sink_wire(&self) -> npnr::WireId {
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self.sink_wire
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}
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pub fn net(&self) -> npnr::NetIndex {
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self.net
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}
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}
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#[derive(Copy, Clone)]
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struct QueuedWire {
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delay: f32,
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congest: f32,
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togo: f32,
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criticality: f32,
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wire: npnr::WireId,
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from_pip: Option<npnr::PipId>,
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}
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impl QueuedWire {
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pub fn new(
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delay: f32,
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congest: f32,
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togo: f32,
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criticality: f32,
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wire: npnr::WireId,
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from_pip: Option<npnr::PipId>,
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) -> Self {
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Self {
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delay,
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congest,
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togo,
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criticality,
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wire,
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from_pip,
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}
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}
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fn score(&self) -> f32 {
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(self.criticality * self.delay) + ((1.0 - self.criticality) * self.congest)
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}
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}
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impl PartialEq for QueuedWire {
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fn eq(&self, other: &Self) -> bool {
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self.delay == other.delay
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&& self.congest == other.congest
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&& self.togo == other.togo
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&& self.wire == other.wire
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}
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}
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impl Eq for QueuedWire {}
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impl Ord for QueuedWire {
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fn cmp(&self, other: &Self) -> std::cmp::Ordering {
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let me = self.score() + self.togo;
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let other = other.score() + other.togo;
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other.total_cmp(&me)
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}
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}
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impl PartialOrd for QueuedWire {
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fn partial_cmp(&self, other: &Self) -> Option<std::cmp::Ordering> {
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Some(self.cmp(other))
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}
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}
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struct PerNetData {
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wires: HashMap<WireId, (PipId, u32)>,
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done_sinks: HashSet<WireId>,
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}
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struct PerWireData {
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wire: WireId,
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curr_cong: u32,
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hist_cong: f32,
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unavailable: bool,
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reserved_net: Option<NetIndex>,
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pip_fwd: PipId,
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visited_fwd: bool,
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pip_bwd: PipId,
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visited_bwd: bool,
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}
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pub struct RouterThread<'a> {
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box_ne: partition::Coord,
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box_sw: partition::Coord,
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arcs: &'a [Arc],
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id: &'a str,
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progress: &'a MultiProgress,
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}
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impl<'a> RouterThread<'a> {
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pub fn new(
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box_ne: partition::Coord,
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box_sw: partition::Coord,
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arcs: &'a [Arc],
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id: &'a str,
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progress: &'a MultiProgress,
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) -> Self {
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Self {
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box_ne,
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box_sw,
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arcs,
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id,
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progress,
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}
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}
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}
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pub struct Router {
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pressure: f32,
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history: f32,
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nets: Vec<PerNetData>,
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wire_to_idx: HashMap<WireId, u32>,
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flat_wires: Vec<PerWireData>,
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dirty_wires: Vec<u32>,
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}
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impl Router {
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pub fn new(nets: &npnr::Nets, wires: &[npnr::WireId], pressure: f32, history: f32) -> Self {
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let mut net_vec = Vec::new();
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let mut flat_wires = Vec::new();
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let mut wire_to_idx = HashMap::new();
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for _ in 0..nets.len() {
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net_vec.push(PerNetData {
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wires: HashMap::new(),
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done_sinks: HashSet::new(),
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});
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}
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for (idx, &wire) in wires.iter().enumerate() {
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flat_wires.push(PerWireData {
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wire,
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curr_cong: 0,
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hist_cong: 0.0,
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unavailable: false,
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reserved_net: None,
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pip_fwd: PipId::null(),
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visited_fwd: false,
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pip_bwd: PipId::null(),
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visited_bwd: false,
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});
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wire_to_idx.insert(wire, idx as u32);
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}
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Self {
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pressure,
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history,
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nets: net_vec,
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wire_to_idx: HashMap::new(),
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flat_wires: Vec::new(),
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dirty_wires: Vec::new(),
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}
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}
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pub fn route(&mut self, ctx: &npnr::Context, nets: &npnr::Nets, this: &RouterThread) {
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let mut delay = HashMap::new();
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for arc in this.arcs {
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delay.insert(arc, 1.0_f32);
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}
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let start = Instant::now();
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let mut max_delay = 1.0;
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let mut least_overuse = usize::MAX;
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let mut iters_since_improvement = 0;
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let mut route_arcs = Vec::from_iter(this.arcs.iter());
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let progress = this.progress.add(ProgressBar::new(0));
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progress.set_style(
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ProgressStyle::with_template("[{elapsed}] [{bar:40.magenta/red}] {msg:30!}")
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.unwrap()
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.progress_chars("━╸ "),
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);
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let mut iterations = 0;
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loop {
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iterations += 1;
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progress.set_position(0);
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progress.set_length(route_arcs.len() as u64);
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for arc in route_arcs.iter().sorted_by(|&i, &j| {
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(delay.get(j).unwrap() / max_delay).total_cmp(&(delay.get(i).unwrap() / max_delay))
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}) {
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let name = ctx.name_of(arc.name).to_str().unwrap();
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progress.inc(1);
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let criticality = (delay.get(arc).unwrap() / max_delay).min(0.99).powf(2.5) + 0.1;
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progress.set_message(format!("{} @ {}: {}", this.id, iterations, name));
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*delay.get_mut(arc).unwrap() = self.route_arc(ctx, nets, arc, criticality);
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}
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let mut overused = HashSet::new();
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for wd in self.flat_wires.iter_mut().filter(|wd| wd.curr_cong > 1) {
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overused.insert(wd.wire);
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wd.hist_cong += (wd.curr_cong as f32) * self.history;
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}
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if overused.is_empty() {
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break;
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} else if overused.len() < least_overuse {
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least_overuse = overused.len();
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iters_since_improvement = 0;
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progress.println(format!(
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"{} @ {}: {} wires overused {}",
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this.id,
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iterations,
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overused.len(),
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"(new best)".bold()
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));
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} else {
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iters_since_improvement += 1;
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progress.println(format!(
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"{} @ {}: {} wires overused",
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this.id,
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iterations,
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overused.len()
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));
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}
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let mut next_arcs = Vec::new();
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for arc in this.arcs {
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for wire in self.nets[arc.net.into_inner() as usize].wires.keys() {
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if overused.contains(wire) {
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next_arcs.push(arc);
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}
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}
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}
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for &arc in &route_arcs {
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self.ripup_arc(ctx, arc);
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}
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for net in &mut self.nets {
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net.done_sinks.clear();
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}
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if iters_since_improvement > 50 {
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iters_since_improvement = 0;
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least_overuse = usize::MAX;
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progress.println(format!(
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"{} @ {}: {}",
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this.id,
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iterations,
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"bored; rerouting everything".bold()
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));
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route_arcs = Vec::from_iter(this.arcs.iter());
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} else {
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route_arcs = next_arcs;
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}
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max_delay = this
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.arcs
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.iter()
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.map(|arc| *delay.get(arc).unwrap())
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.reduce(f32::max)
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.unwrap();
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}
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let now = (Instant::now() - start).as_secs_f32();
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progress.println(format!(
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"{} @ {}: {} in {:.0}m{:.03}s",
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this.id,
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iterations,
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"routing complete".green(),
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now / 60.0,
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now % 60.0
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));
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progress.finish_and_clear();
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}
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fn can_visit_pip(&self, ctx: &npnr::Context, nets: &npnr::Nets, arc: &Arc, pip: PipId) -> bool {
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let wire = ctx.pip_dst_wire(pip);
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let sink = *self.wire_to_idx.get(&wire).unwrap();
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let nd = &self.nets[arc.net().into_inner() as usize];
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let nwd = &self.flat_wires[sink as usize];
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/*let pip_coord = partition::Coord::from(ctx.pip_location(pip));
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if pip_coord.is_north_of(&self.box_ne) || pip_coord.is_east_of(&self.box_ne) {
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return false;
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}
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if pip_coord.is_south_of(&self.box_sw) || pip_coord.is_west_of(&self.box_sw) {
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return false;
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}*/
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if !ctx.pip_avail_for_net(pip, nets.net_from_index(arc.net())) {
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return false;
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}
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if nwd.unavailable {
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return false;
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}
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if let Some(net) = nwd.reserved_net && net != arc.net() {
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return false;
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}
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// Don't allow the same wire to be bound to the same net with a different driving pip
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if let Some((found_pip, _)) = nd.wires.get(&wire) && *found_pip != pip {
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return false;
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}
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true
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}
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fn step<F1, F2, F3, F4, F5, I>(
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&mut self,
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ctx: &npnr::Context,
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nets: &npnr::Nets,
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arc: &Arc,
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criticality: f32,
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queue: &mut BinaryHeap<QueuedWire>,
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midpoint: &mut Option<u32>,
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target: WireId,
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was_visited: F1,
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set_visited: F2,
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is_done: F3,
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pip_iter: F4,
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pip_wire: F5,
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) -> bool
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where
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F1: Fn(&Self, u32) -> bool,
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F2: Fn(&mut Self, u32, PipId),
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F3: Fn(&Self, u32) -> bool,
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F4: Fn(&npnr::Context, WireId) -> I,
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F5: Fn(&npnr::Context, PipId) -> WireId,
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I: Iterator<Item = PipId>,
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{
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if let Some(source) = queue.pop() {
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let source_idx = *self.wire_to_idx.get(&source.wire).unwrap();
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if was_visited(self, source_idx) {
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return true;
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}
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if let Some(pip) = source.from_pip {
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set_visited(self, source_idx, pip);
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}
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if is_done(self, source_idx) {
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*midpoint = Some(source_idx);
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return false;
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}
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for pip in pip_iter(ctx, source.wire) {
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if !self.can_visit_pip(ctx, nets, arc, pip) {
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continue;
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}
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let wire = pip_wire(ctx, pip);
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let sink = *self.wire_to_idx.get(&wire).unwrap();
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if was_visited(self, sink) {
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continue;
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}
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set_visited(self, sink, pip);
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let nwd = &self.flat_wires[sink as usize];
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let node_delay = ctx.pip_delay(pip) + ctx.wire_delay(wire) + ctx.delay_epsilon();
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let sum_delay = source.delay + node_delay;
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let congest = source.congest
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+ (node_delay + nwd.hist_cong) * (1.0 + (nwd.curr_cong as f32 * self.pressure));
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let qw = QueuedWire::new(
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sum_delay,
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congest,
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ctx.estimate_delay(wire, target),
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criticality,
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wire,
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Some(pip),
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);
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queue.push(qw);
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}
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return true;
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}
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false
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}
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fn route_arc(
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&mut self,
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ctx: &npnr::Context,
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nets: &npnr::Nets,
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arc: &Arc,
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criticality: f32,
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) -> f32 {
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if arc.source_wire == arc.sink_wire {
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return 0.0;
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}
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let mut fwd_queue = BinaryHeap::new();
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fwd_queue.push(QueuedWire::new(
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0.0,
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0.0,
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ctx.estimate_delay(arc.source_wire, arc.sink_wire),
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criticality,
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arc.source_wire,
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None,
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));
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let mut bwd_queue = BinaryHeap::new();
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bwd_queue.push(QueuedWire::new(
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0.0,
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0.0,
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ctx.estimate_delay(arc.source_wire, arc.sink_wire),
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criticality,
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arc.sink_wire,
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None,
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));
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let mut midpoint = None;
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let source_wire = *self.wire_to_idx.get(&arc.source_wire).unwrap();
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let sink_wire = *self.wire_to_idx.get(&arc.sink_wire).unwrap();
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self.dirty_wires.push(source_wire);
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self.dirty_wires.push(sink_wire);
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let nd = &self.nets[arc.net().into_inner() as usize];
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if nd.done_sinks.contains(&arc.sink_wire()) {
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midpoint = Some(*self.wire_to_idx.get(&arc.sink_wire).unwrap());
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let mut wire = arc.sink_wire();
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while wire != arc.source_wire() {
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let driver = nd.wires.get(&wire).unwrap().0;
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self.set_visited_fwd(self.wire_to_idx[&wire], driver);
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wire = ctx.pip_src_wire(driver);
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}
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} else {
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while midpoint.is_none() {
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// Step forward
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if !self.step(
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ctx,
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nets,
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arc,
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criticality,
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&mut fwd_queue,
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&mut midpoint,
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arc.sink_wire,
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Self::was_visited_fwd,
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Self::set_visited_fwd,
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Self::was_visited_bwd,
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npnr::Context::get_downhill_pips,
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npnr::Context::pip_dst_wire,
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) {
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break;
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}
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// Step backward
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if !self.step(
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ctx,
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nets,
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arc,
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criticality,
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&mut bwd_queue,
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&mut midpoint,
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arc.source_wire,
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Self::was_visited_bwd,
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Self::set_visited_bwd,
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Self::was_visited_fwd,
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npnr::Context::get_uphill_pips,
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npnr::Context::pip_src_wire,
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) {
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break;
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}
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self.flat_wires[source_wire as usize].visited_fwd = true;
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self.flat_wires[sink_wire as usize].visited_bwd = true;
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}
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}
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assert!(
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midpoint.is_some(),
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"didn't find sink wire for net {} between {} and {}",
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ctx.name_of(arc.name).to_str().unwrap(),
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ctx.name_of_wire(arc.source_wire).to_str().unwrap(),
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ctx.name_of_wire(arc.sink_wire).to_str().unwrap(),
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);
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let mut wire = midpoint.unwrap();
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let mut calculated_delay = 0.0;
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while wire != source_wire {
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let pip = self.flat_wires[wire as usize].pip_fwd;
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assert!(pip != PipId::null());
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let node_delay = ctx.pip_delay(pip)
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+ ctx.wire_delay(self.flat_wires[wire as usize].wire)
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+ ctx.delay_epsilon();
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calculated_delay += node_delay;
|
|
|
|
self.bind_pip_internal(arc.net(), wire, pip);
|
|
wire = *self.wire_to_idx.get(&ctx.pip_src_wire(pip)).unwrap();
|
|
}
|
|
let mut wire = midpoint.unwrap();
|
|
while wire != sink_wire {
|
|
let pip = self.flat_wires[wire as usize].pip_bwd;
|
|
assert!(pip != PipId::null());
|
|
// do note that the order is inverted from the fwd loop
|
|
wire = *self.wire_to_idx.get(&ctx.pip_dst_wire(pip)).unwrap();
|
|
|
|
let node_delay = ctx.pip_delay(pip)
|
|
+ ctx.wire_delay(self.flat_wires[wire as usize].wire)
|
|
+ ctx.delay_epsilon();
|
|
calculated_delay += node_delay;
|
|
|
|
self.bind_pip_internal(arc.net(), wire, pip);
|
|
}
|
|
let nd = &mut self.nets[arc.net().into_inner() as usize];
|
|
nd.done_sinks.insert(arc.sink_wire());
|
|
|
|
self.reset_wires();
|
|
|
|
calculated_delay
|
|
}
|
|
|
|
fn was_visited_fwd(&self, wire: u32) -> bool {
|
|
self.flat_wires[wire as usize].visited_fwd
|
|
}
|
|
|
|
fn was_visited_bwd(&self, wire: u32) -> bool {
|
|
self.flat_wires[wire as usize].visited_bwd
|
|
}
|
|
|
|
fn set_visited_fwd(&mut self, wire: u32, pip: PipId) {
|
|
let wd = &mut self.flat_wires[wire as usize];
|
|
if !wd.visited_fwd {
|
|
self.dirty_wires.push(wire);
|
|
}
|
|
wd.pip_fwd = pip;
|
|
wd.visited_fwd = true;
|
|
}
|
|
|
|
fn set_visited_bwd(&mut self, wire: u32, pip: PipId) {
|
|
let wd = &mut self.flat_wires[wire as usize];
|
|
if !wd.visited_bwd {
|
|
self.dirty_wires.push(wire);
|
|
}
|
|
wd.pip_bwd = pip;
|
|
wd.visited_bwd = true;
|
|
}
|
|
|
|
fn bind_pip_internal(&mut self, netindex: NetIndex, wire: u32, pip: PipId) {
|
|
let wireid = self.flat_wires[wire as usize].wire;
|
|
let net = &mut self.nets[netindex.into_inner() as usize];
|
|
if let Some((bound_pip, usage)) = net.wires.get_mut(&wireid) {
|
|
assert!(*bound_pip == pip);
|
|
*usage += 1;
|
|
} else {
|
|
net.wires.insert(wireid, (pip, 1));
|
|
self.flat_wires[wire as usize].curr_cong += 1;
|
|
}
|
|
}
|
|
|
|
fn unbind_pip_internal(&mut self, net: NetIndex, wire: WireId) {
|
|
let net = net.into_inner() as usize;
|
|
let wireidx = *self.wire_to_idx.get(&wire).unwrap() as usize;
|
|
let (_pip, usage) = self.nets[net].wires.get_mut(&wire).unwrap();
|
|
*usage -= 1;
|
|
if *usage == 0 {
|
|
self.flat_wires[wireidx].curr_cong -= 1;
|
|
self.nets[net].wires.remove(&wire);
|
|
}
|
|
}
|
|
|
|
fn ripup_arc(&mut self, ctx: &npnr::Context, arc: &Arc) {
|
|
let net = arc.net().into_inner() as usize;
|
|
let source_wire = arc.source_wire;
|
|
let mut wire = arc.sink_wire;
|
|
while wire != source_wire {
|
|
let pip = self.nets[net].wires.get(&wire).unwrap().0;
|
|
assert!(pip != PipId::null());
|
|
self.unbind_pip_internal(arc.net(), wire);
|
|
wire = ctx.pip_src_wire(pip);
|
|
}
|
|
}
|
|
|
|
fn reset_wires(&mut self) {
|
|
for &wire in &self.dirty_wires {
|
|
self.flat_wires[wire as usize].pip_fwd = PipId::null();
|
|
self.flat_wires[wire as usize].visited_fwd = false;
|
|
self.flat_wires[wire as usize].pip_bwd = PipId::null();
|
|
self.flat_wires[wire as usize].visited_bwd = false;
|
|
}
|
|
self.dirty_wires.clear();
|
|
}
|
|
}
|