36 lines
592 B
Verilog
36 lines
592 B
Verilog
module LUT4 #(
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parameter [15:0] INIT = 0
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) (
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input [3:0] I,
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output F
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);
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wire [7:0] s3 = I[3] ? INIT[15:8] : INIT[7:0];
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wire [3:0] s2 = I[2] ? s3[ 7:4] : s3[3:0];
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wire [1:0] s1 = I[1] ? s2[ 3:2] : s2[1:0];
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assign F = I[0] ? s1[1] : s1[0];
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endmodule
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module DFF (
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input CLK, D,
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output reg Q
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);
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initial Q = 1'b0;
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always @(posedge CLK)
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Q <= D;
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endmodule
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module INBUF (
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input PAD,
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output O,
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);
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assign O = PAD;
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endmodule
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module OUTBUF (
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output PAD,
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input I,
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);
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assign PAD = I;
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endmodule
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