028be1462a
* apicula: add support for magic sip pins * fix nullptr check * DDR fix by xiwang * WIP support for setting the iostd * add iostd
280 lines
12 KiB
C++
280 lines
12 KiB
C++
#include <boost/algorithm/string.hpp>
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#include <regex>
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#include <utility>
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#include "log.h"
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#include "nextpnr.h"
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#include "util.h"
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#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
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#include "himbaechel_constids.h"
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#include "himbaechel_helpers.h"
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#include "cst.h"
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#include "gowin.h"
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NEXTPNR_NAMESPACE_BEGIN
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struct GowinCstReader
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{
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Context *ctx;
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std::istream ∈
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GowinCstReader(Context *ctx, std::istream &in) : ctx(ctx), in(in) {};
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const PadInfoPOD *pinLookup(const PadInfoPOD *list, const size_t len, const IdString idx)
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{
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for (size_t i = 0; i < len; i++) {
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const PadInfoPOD *pin = &list[i];
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if (IdString(pin->package_pin) == idx) {
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return pin;
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}
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}
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return nullptr;
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}
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Loc getLoc(std::smatch match, int maxX, int maxY)
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{
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int col = std::stoi(match[2]);
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int row = 1; // Top
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std::string side = match[1].str();
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if (side == "R") {
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row = col;
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col = maxX;
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} else if (side == "B") {
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row = maxY;
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} else if (side == "L") {
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row = col;
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col = 1;
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}
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int z = match[3].str()[0] - 'A' + BelZ::IOBA_Z;
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return Loc(col - 1, row - 1, z);
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}
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BelId getConstrainedHCLKBel(std::smatch match, int maxX, int maxY)
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{
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int idx = std::stoi(match[3]);
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int bel_z = BelZ::CLKDIV_0_Z + 2 * idx;
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std::string side = match[2].str();
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bool lr = (side == "LEFT") || (side == "RIGHT");
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int y_coord = (side == "BOTTOM") ? maxY - 1 : 0;
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int x_coord = (side == "RIGHT") ? maxX - 1 : 0;
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for (auto &bel : ctx->getBelsInBucket(ctx->getBelBucketForCellType(id_CLKDIV))) {
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auto this_loc = ctx->getBelLocation(bel);
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if (lr && this_loc.x == x_coord && this_loc.z == bel_z && this_loc.y != 0 &&
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this_loc.y != maxY - 1) // left or right side
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return bel;
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else if (!lr && this_loc.y == y_coord && this_loc.z == bel_z) // top or bottom side
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return bel;
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}
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return BelId();
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}
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bool run(void)
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{
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pool<std::pair<IdString, IdStringList>> constrained_cells;
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auto debug_cell = [this, &constrained_cells](IdString cellId, IdStringList belId) {
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if (ctx->debug) {
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constrained_cells.insert(std::make_pair(cellId, belId));
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}
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};
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log_info("Reading constraints...\n");
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try {
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// If two locations are specified separated by commas (for differential I/O buffers),
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// only the first location is actually recognized and used.
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// And pin A will be Positive and pin B will be Negative in any case.
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std::regex iobre = std::regex("IO_LOC +\"([^\"]+)\" +([^ ,;]+)(, *[^ ;]+)? *;.*[\\s\\S]*");
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std::regex portre = std::regex("IO_PORT +\"([^\"]+)\" +([^;]+;).*[\\s\\S]*");
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std::regex port_attrre = std::regex("([^ =;]+=[^ =;]+) *([^;]*;)");
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std::regex iobelre = std::regex("IO([TRBL])([0-9]+)\\[?([A-Z])\\]?");
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std::regex inslocre =
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std::regex("INS_LOC +\"([^\"]+)\" +R([0-9]+)C([0-9]+)\\[([0-9])\\]\\[([AB])\\] *;.*[\\s\\S]*");
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std::regex hclkre =
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std::regex("INS_LOC +\"([^\"]+)\" +(TOP|RIGHT|BOTTOM|LEFT)SIDE\\[([0,1])\\] *;*[\\s\\S]*");
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std::regex clockre = std::regex("CLOCK_LOC +\"([^\"]+)\" +BUF([GS])(\\[([0-7])\\])?[^;]*;.*[\\s\\S]*");
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std::smatch match, match_attr, match_pinloc;
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std::string line, pinline;
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std::vector<IdStringList> constrained_clkdivs;
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enum
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{
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ioloc,
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ioport,
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insloc,
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clock,
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hclk
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} cst_type;
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while (!in.eof()) {
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std::getline(in, line);
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cst_type = ioloc;
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if (!std::regex_match(line, match, iobre)) {
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if (std::regex_match(line, match, portre)) {
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cst_type = ioport;
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} else {
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if (std::regex_match(line, match, clockre)) {
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cst_type = clock;
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} else {
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if (std::regex_match(line, match, inslocre)) {
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cst_type = insloc;
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} else {
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if (std::regex_match(line, match, hclkre)) {
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cst_type = hclk;
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} else {
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if ((!line.empty()) && (line.rfind("//", 0) == std::string::npos)) {
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log_warning("Invalid constraint: %s\n", line.c_str());
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}
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continue;
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}
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}
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}
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}
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}
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IdString net = ctx->id(match[1]);
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auto it = ctx->cells.find(net);
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if (cst_type != clock && it == ctx->cells.end()) {
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log_info("Cell %s not found\n", net.c_str(ctx));
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continue;
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}
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switch (cst_type) {
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case clock: { // CLOCK name BUFG|S=#
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std::string which_clock = match[2];
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std::string lw = match[4];
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int lw_idx = -1;
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if (lw.length() > 0) {
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lw_idx = atoi(lw.c_str());
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log_info("lw_idx:%d\n", lw_idx);
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}
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if (which_clock.at(0) == 'S') {
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auto ni = ctx->nets.find(net);
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if (ni == ctx->nets.end()) {
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log_info("Net %s not found\n", net.c_str(ctx));
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continue;
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}
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// if (!allocate_longwire(ni->second.get(), lw_idx)) {
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log_info("Can't use the long wires. The %s network will use normal routing.\n", net.c_str(ctx));
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//}
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} else {
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auto ni = ctx->nets.find(net);
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if (ni == ctx->nets.end()) {
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log_info("Net %s not found\n", net.c_str(ctx));
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continue;
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}
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if (ctx->debug) {
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log_info("Mark net '%s' as CLOCK\n", net.c_str(ctx));
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}
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// XXX YES for now. May be put the number here
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ni->second->attrs[id_CLOCK] = Property(std::string("YES"));
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}
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} break;
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case ioloc: { // IO_LOC name pin
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IdString pinname = ctx->id(match[2]);
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pinline = match[2];
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const PadInfoPOD *belname =
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pinLookup(ctx->package_info->pads.get(), ctx->package_info->pads.ssize(), pinname);
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if (belname != nullptr) {
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IdStringList bel = IdStringList::concat(IdString(belname->tile), IdString(belname->bel));
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it->second->setAttr(IdString(ID_BEL), bel.str(ctx));
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debug_cell(it->second->name, bel);
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} else {
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if (std::regex_match(pinline, match_pinloc, iobelre)) {
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// may be it's IOx#[AB] style?
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Loc loc = getLoc(match_pinloc, ctx->getGridDimX(), ctx->getGridDimY());
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BelId bel = ctx->getBelByLocation(loc);
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if (bel == BelId()) {
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log_error("Pin %s not found (TRBL style). \n", pinline.c_str());
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}
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it->second->setAttr(IdString(ID_BEL), std::string(ctx->nameOfBel(bel)));
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debug_cell(it->second->name, ctx->getBelName(bel));
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} else {
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log_error("Pin %s not found (pin# style)\n", pinname.c_str(ctx));
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}
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}
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} break;
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case hclk: {
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IdString cell_type = it->second->type;
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if (cell_type != id_CLKDIV) {
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log_error("Unsupported or invalid cell type %s for hclk\n", cell_type.c_str(ctx));
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}
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BelId hclk_bel = getConstrainedHCLKBel(match, ctx->getGridDimX(), ctx->getGridDimY());
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if (hclk_bel != BelId()) {
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auto hclk_bel_name = ctx->getBelName(hclk_bel);
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if (std::find(constrained_clkdivs.begin(), constrained_clkdivs.end(), hclk_bel_name) !=
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constrained_clkdivs.end()) {
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log_error("Only one CLKDIV can be placed at %sSIDE[%s]\n", match[2].str().c_str(),
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match[3].str().c_str());
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}
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constrained_clkdivs.push_back(hclk_bel_name);
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it->second->setAttr(id_BEL, ctx->getBelName(hclk_bel).str(ctx));
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debug_cell(it->second->name, ctx->getBelName(hclk_bel));
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} else {
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log_error("No Bel of type CLKDIV found at constrained location %sSIDE[%s]\n",
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match[2].str().c_str(), match[3].str().c_str());
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}
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} break;
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default: { // IO_PORT attr=value
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std::string attr_val = match[2];
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while (std::regex_match(attr_val, match_attr, port_attrre)) {
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std::string attr = "&";
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attr += match_attr[1];
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boost::algorithm::to_upper(attr);
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it->second->setAttr(ctx->id(attr), 1);
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attr_val = match_attr[2];
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}
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}
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}
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}
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if (ctx->debug) {
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for (auto &cell : constrained_cells) {
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log_info("Cell %s is constrained to %s\n", cell.first.c_str(ctx), cell.second.str(ctx).c_str());
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}
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}
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return true;
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} catch (log_execution_error_exception) {
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return false;
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}
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}
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};
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static void add_sip_constraints(Context *ctx, const Extra_package_data_POD *extra) {
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for(auto cst : extra->cst) {
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auto it = ctx->cells.find(IdString(cst.net));
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if (it == ctx->cells.end()) {
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log_info("Cell %s not found\n", IdString(cst.net).c_str(ctx));
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continue;
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}
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Loc loc = Loc(cst.col, cst.row, cst.bel);
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BelId bel = ctx->getBelByLocation(loc);
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if (bel == BelId()) {
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log_error("Pin not found.\n");
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}
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it->second->setAttr(IdString(ID_BEL), std::string(ctx->nameOfBel(bel)));
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if(cst.iostd > 0) {
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std::string attr = "&IO_TYPE=";
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attr += IdString(cst.iostd).c_str(ctx);
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boost::algorithm::to_upper(attr);
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it->second->setAttr(ctx->id(attr), 1);
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}
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}
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}
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bool gowin_apply_constraints(Context *ctx, std::istream &in)
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{
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// implicit constraints from SiP pins
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if(!ctx->package_info->extra_data.is_null()) {
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const Extra_package_data_POD *extra = reinterpret_cast<const Extra_package_data_POD *>(ctx->package_info->extra_data.get());
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add_sip_constraints(ctx, extra);
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}
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GowinCstReader reader(ctx, in);
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return reader.run();
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}
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NEXTPNR_NAMESPACE_END
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