df99b4ff6c
When there is a constraint conflict while placing IOs, the user gets an error message such as ERROR: Bel 'X0/Y27/io1' of type 'SB_IO' is not valid for cell 'my_pin' of type 'SB_IO' While this identifies the problematic cell, it does not explain why there is a problem. Add some verbose messages to allow users to determine where the problem is. This can result in something like Info: Net '$PACKER_VCC_NET' for cell 'my_pin' conflicts with net 'ce' for 'ce_pin' which provides something actionable. Signed-off-by: Sean Anderson <seanga2@gmail.com>
217 lines
8.7 KiB
C++
217 lines
8.7 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2018 gatecat <gatecat@ds0.me>
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* Copyright (C) 2018 Serge Bazanski <q3k@q3k.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "cells.h"
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#include "nextpnr.h"
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#include "util.h"
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#include <boost/range/iterator_range.hpp>
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NEXTPNR_NAMESPACE_BEGIN
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bool Arch::logic_cells_compatible(const CellInfo **it, const size_t size) const
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{
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bool dffs_exist = false, dffs_neg = false;
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const NetInfo *cen = nullptr, *clk = nullptr, *sr = nullptr;
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int locals_count = 0;
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for (auto cell : boost::make_iterator_range(it, it + size)) {
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NPNR_ASSERT(cell->type == id_ICESTORM_LC);
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if (cell->lcInfo.dffEnable) {
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if (!dffs_exist) {
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dffs_exist = true;
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cen = cell->lcInfo.cen;
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clk = cell->lcInfo.clk;
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sr = cell->lcInfo.sr;
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if (cen != nullptr && !cen->is_global)
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locals_count++;
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if (clk != nullptr && !clk->is_global)
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locals_count++;
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if (sr != nullptr && !sr->is_global)
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locals_count++;
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if (cell->lcInfo.negClk) {
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dffs_neg = true;
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}
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} else {
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if (cen != cell->lcInfo.cen)
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return false;
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if (clk != cell->lcInfo.clk)
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return false;
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if (sr != cell->lcInfo.sr)
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return false;
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if (dffs_neg != cell->lcInfo.negClk)
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return false;
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}
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}
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locals_count += cell->lcInfo.inputCount;
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}
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return locals_count <= 32;
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}
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static inline bool _io_pintype_need_clk_in(unsigned pin_type) { return (pin_type & 0x01) == 0x00; }
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static inline bool _io_pintype_need_clk_out(unsigned pin_type)
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{
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return ((pin_type & 0x30) == 0x30) || ((pin_type & 0x3c) && ((pin_type & 0x0c) != 0x08));
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}
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static inline bool _io_pintype_need_clk_en(unsigned pin_type)
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{
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return _io_pintype_need_clk_in(pin_type) || _io_pintype_need_clk_out(pin_type);
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}
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bool Arch::isBelLocationValid(BelId bel, bool explain_invalid) const
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{
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if (getBelType(bel) == id_ICESTORM_LC) {
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std::array<const CellInfo *, 8> bel_cells;
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size_t num_cells = 0;
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Loc bel_loc = getBelLocation(bel);
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for (auto bel_other : getBelsByTile(bel_loc.x, bel_loc.y)) {
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CellInfo *ci_other = getBoundBelCell(bel_other);
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if (ci_other != nullptr)
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bel_cells[num_cells++] = ci_other;
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}
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return logic_cells_compatible(bel_cells.data(), num_cells);
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} else {
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const CellInfo *cell = getBoundBelCell(bel);
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if (cell == nullptr)
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return true;
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else if (cell->type == id_SB_IO) {
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// Do not allow placement of input SB_IOs on blocks where there a PLL is outputting to.
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// Find shared PLL by looking for driving bel siblings from D_IN_0
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// that are a PLL clock output.
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auto wire = getBelPinWire(bel, id_D_IN_0);
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for (auto pin : getWireBelPins(wire)) {
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if (pin.pin.in(id_PLLOUT_A, id_PLLOUT_B)) {
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// Is there a PLL there ?
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const CellInfo *pll_cell = getBoundBelCell(pin.bel);
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if (pll_cell == nullptr)
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break;
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// Is that port actually used ?
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if ((pin.pin == id_PLLOUT_B) && !is_sb_pll40_dual(this, pll_cell))
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break;
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// Is that SB_IO used at an input ?
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if ((cell->getPort(id_D_IN_0) == nullptr) && (cell->getPort(id_D_IN_1) == nullptr))
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break;
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// Are we perhaps a PAD INPUT Bel that can be placed here?
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if (str_or_default(pll_cell->attrs, id_BEL_PAD_INPUT, "") == getBelName(bel).str(getCtx()))
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return true;
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// Conflict
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if (explain_invalid)
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log_nonfatal_error("Cell '%s' conflicts with PLL cell '%s'\n", nameOf(cell), nameOf(pll_cell));
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return false;
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}
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}
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Loc ioLoc = getBelLocation(bel);
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Loc compLoc = ioLoc;
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compLoc.z = 1 - compLoc.z;
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// Check LVDS pairing
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if (cell->ioInfo.lvds) {
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// Check correct z and complement location is free
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if (ioLoc.z != 0) {
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if (explain_invalid)
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log_nonfatal_error("Bel '%s' can't be used for LVDS\n", getCtx()->nameOfBel(bel));
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return false;
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}
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BelId compBel = getBelByLocation(compLoc);
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CellInfo *compCell = getBoundBelCell(compBel);
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if (compCell) {
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if (explain_invalid)
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log_nonfatal_error("Cell '%s' LVDS complement occupied by cell '%s'\n", nameOf(cell),
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nameOf(compCell));
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return false;
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}
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} else {
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// Check LVDS IO is not placed at complement location
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BelId compBel = getBelByLocation(compLoc);
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const CellInfo *compCell = getBoundBelCell(compBel);
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if (compCell && compCell->ioInfo.lvds) {
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if (explain_invalid)
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log_nonfatal_error("Cell '%s' can't occupy LVDS complement of cell '%s'\n", nameOf(cell),
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nameOf(compCell));
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return false;
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}
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// Check for conflicts on shared nets
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// - CLOCK_ENABLE
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// - OUTPUT_CLK
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// - INPUT_CLK
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if (compCell) {
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bool use[6] = {
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_io_pintype_need_clk_in(cell->ioInfo.pintype),
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_io_pintype_need_clk_in(compCell->ioInfo.pintype),
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_io_pintype_need_clk_out(cell->ioInfo.pintype),
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_io_pintype_need_clk_out(compCell->ioInfo.pintype),
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_io_pintype_need_clk_en(cell->ioInfo.pintype),
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_io_pintype_need_clk_en(compCell->ioInfo.pintype),
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};
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const NetInfo *nets[] = {
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cell->getPort(id_INPUT_CLK), compCell->getPort(id_INPUT_CLK),
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cell->getPort(id_OUTPUT_CLK), compCell->getPort(id_OUTPUT_CLK),
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cell->getPort(id_CLOCK_ENABLE), compCell->getPort(id_CLOCK_ENABLE),
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};
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for (int i = 0; i < 6; i++)
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if (use[i] && (nets[i] != nets[i ^ 1]) && (use[i ^ 1] || (nets[i ^ 1] != nullptr))) {
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if (explain_invalid)
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log_nonfatal_error("Net '%s' for cell '%s' conflicts with net '%s' for '%s'\n",
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nameOf(nets[i]), nameOf(cell), nameOf(nets[i ^ 1]),
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nameOf(compCell));
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return false;
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}
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}
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}
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return get_bel_package_pin(bel) != "";
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} else if (cell->type == id_SB_GB) {
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if (cell->gbInfo.forPadIn)
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return true;
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NPNR_ASSERT(cell->ports.at(id_GLOBAL_BUFFER_OUTPUT).net != nullptr);
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const NetInfo *net = cell->ports.at(id_GLOBAL_BUFFER_OUTPUT).net;
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int glb_id = get_driven_glb_netwk(bel);
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if (net->is_reset && net->is_enable)
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return false;
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else if (net->is_reset)
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return (glb_id % 2) == 0;
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else if (net->is_enable)
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return (glb_id % 2) == 1;
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else
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return true;
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} else {
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// TODO: IO cell clock checks
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return true;
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}
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}
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}
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NEXTPNR_NAMESPACE_END
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