10a5a44b81
DQCE and DCS primitives are added.
DQCE allows the internal logic to enable or disable the clock network in
the quadrant. When clock network is disabled, all logic drivern by this
clock is no longer toggled, thus reducing the total power consumtion of
the device.
DCS allows you to select one of four sources for two clock wires (6 and 7).
Wires 6 and 7 have not been used up to this point.
Since "hardware" primitives operate strictly in their own quadrants,
user-specified primitives are converted into one or more "hardware"
primitives as needed.
Also:
- minor edits to make the most of helper functions like connectPorts()
- when creating bases, the corresponding constants are assigned to the
VCC and GND wires, but for now huge nodes are used because, for an
unknown reason, the constants mechanism makes large examples
inoperable. So for now we remain on the nodes.
Compatible with older Apicula databases.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
708 lines
25 KiB
C++
708 lines
25 KiB
C++
#include <regex>
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#include "himbaechel_api.h"
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#include "himbaechel_helpers.h"
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#include "log.h"
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#include "nextpnr.h"
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#define GEN_INIT_CONSTIDS
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#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
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#include "himbaechel_constids.h"
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#include "cst.h"
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#include "globals.h"
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#include "gowin.h"
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#include "gowin_utils.h"
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#include "pack.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace {
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struct GowinImpl : HimbaechelAPI
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{
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~GowinImpl(){};
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void init_database(Arch *arch) override;
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void init(Context *ctx) override;
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void pack() override;
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void prePlace() override;
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void postPlace() override;
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void preRoute() override;
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void postRoute() override;
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bool isBelLocationValid(BelId bel, bool explain_invalid) const override;
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void notifyBelChange(BelId bel, CellInfo *cell) override;
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// Bel bucket functions
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IdString getBelBucketForCellType(IdString cell_type) const override;
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bool isValidBelForCellType(IdString cell_type, BelId bel) const override;
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// wires
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bool checkPipAvail(PipId pip) const override;
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// Cluster
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bool isClusterStrict(const CellInfo *cell) const { return true; }
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bool getClusterPlacement(ClusterId cluster, BelId root_bel,
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std::vector<std::pair<CellInfo *, BelId>> &placement) const;
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private:
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HimbaechelHelpers h;
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GowinUtils gwu;
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IdString chip;
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IdString partno;
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std::set<BelId> inactive_bels;
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// Validity checking
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struct GowinCellInfo
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{
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// slice info
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const NetInfo *lut_f = nullptr;
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const NetInfo *ff_d = nullptr, *ff_ce = nullptr, *ff_clk = nullptr, *ff_lsr = nullptr;
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const NetInfo *alu_sum = nullptr;
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// dsp info
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const NetInfo *dsp_asign = nullptr, *dsp_bsign = nullptr, *dsp_asel = nullptr, *dsp_bsel = nullptr,
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*dsp_ce = nullptr, *dsp_clk = nullptr, *dsp_reset = nullptr;
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bool dsp_soa_reg;
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};
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std::vector<GowinCellInfo> fast_cell_info;
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void assign_cell_info();
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// dsp control nets
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// Each DSP and each macro has a small set of control wires that are
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// allocated to internal primitives as needed. It is assumed that most
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// primitives use the same signals for CE, CLK and especially RESET, so
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// these wires are few and need to be controlled.
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struct dsp_net_counters
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{
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dict<IdString, int> ce;
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dict<IdString, int> clk;
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dict<IdString, int> reset;
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};
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dict<BelId, dsp_net_counters> dsp_net_cnt;
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dict<BelId, CellInfo *> dsp_bel2cell; // Remember the connection with cells
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// since this information is already lost during unbinding
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void adjust_dsp_pin_mapping(void);
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// bel placement validation
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bool slice_valid(int x, int y, int z) const;
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bool dsp_valid(Loc l, IdString bel_type, bool explain_invalid) const;
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};
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struct GowinArch : HimbaechelArch
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{
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GowinArch() : HimbaechelArch("gowin"){};
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bool match_device(const std::string &device) override { return device.size() > 2 && device.substr(0, 2) == "GW"; }
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std::unique_ptr<HimbaechelAPI> create(const std::string &device, const dict<std::string, std::string> &args)
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{
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return std::make_unique<GowinImpl>();
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}
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} gowinrArch;
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void GowinImpl::init_database(Arch *arch)
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{
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init_uarch_constids(arch);
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const ArchArgs &args = arch->args;
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std::string family;
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if (args.options.count("family")) {
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family = args.options.at("family");
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} else {
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bool GW2 = args.device.rfind("GW2A", 0) == 0;
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if (GW2) {
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log_error("For the GW2A series you need to specify --vopt family=GW2A-18 or --vopt family=GW2A-18C\n");
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} else {
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std::regex devicere = std::regex("GW1N([SZ]?)[A-Z]*-(LV|UV|UX)([0-9])(C?).*");
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std::smatch match;
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if (!std::regex_match(args.device, match, devicere)) {
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log_error("Invalid device %s\n", args.device.c_str());
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}
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family = stringf("GW1N%s-%s", match[1].str().c_str(), match[3].str().c_str());
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if (family.rfind("GW1N-9", 0) == 0) {
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log_error("For the GW1N-9 series you need to specify --vopt family=GW1N-9 or --vopt family=GW1N-9C\n");
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}
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}
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}
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arch->load_chipdb(stringf("gowin/chipdb-%s.bin", family.c_str()));
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// These fields go in the header of the output JSON file and can help
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// gowin_pack support different architectures
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arch->settings[arch->id("packer.arch")] = std::string("himbaechel/gowin");
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arch->settings[arch->id("packer.chipdb")] = family;
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chip = arch->id(family);
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std::string pn = args.device;
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partno = arch->id(pn);
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arch->settings[arch->id("packer.partno")] = pn;
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}
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void GowinImpl::init(Context *ctx)
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{
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h.init(ctx);
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HimbaechelAPI::init(ctx);
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gwu.init(ctx);
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const ArchArgs &args = ctx->getArchArgs();
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// package and speed class
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std::regex speedre = std::regex("(.*)(C[0-9]/I[0-9])$");
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std::smatch match;
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IdString spd;
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IdString package_idx;
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std::string pn = args.device;
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if (std::regex_match(pn, match, speedre)) {
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package_idx = ctx->id(match[1]);
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spd = ctx->id(match[2]);
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} else {
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if (pn.length() > 2 && pn.compare(pn.length() - 2, 2, "ES")) {
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package_idx = ctx->id(pn.substr(pn.length() - 2));
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spd = ctx->id("ES");
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}
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}
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// log_info("packages:%ld\n", ctx->chip_info->packages.ssize());
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for (int i = 0; i < ctx->chip_info->packages.ssize(); ++i) {
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if (IdString(ctx->chip_info->packages[i].name) == package_idx) {
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// log_info("i:%d %s\n", i, package_idx.c_str(ctx));
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ctx->package_info = &ctx->chip_info->packages[i];
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break;
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}
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}
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if (ctx->package_info == nullptr) {
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log_error("No package for partnumber %s\n", partno.c_str(ctx));
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}
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// constraints
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if (args.options.count("cst")) {
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ctx->settings[ctx->id("cst.filename")] = args.options.at("cst");
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}
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}
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// We do not allow the use of global wires that bypass a special router.
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bool GowinImpl::checkPipAvail(PipId pip) const
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{
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return (ctx->getWireConstantValue(ctx->getPipSrcWire(pip)) != IdString()) || (!gwu.is_global_pip(pip));
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}
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void GowinImpl::pack()
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{
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if (ctx->settings.count(ctx->id("cst.filename"))) {
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std::string filename = ctx->settings[ctx->id("cst.filename")].as_string();
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std::ifstream in(filename);
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if (!in) {
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log_error("failed to open CST file '%s'\n", filename.c_str());
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}
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if (!gowin_apply_constraints(ctx, in)) {
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log_error("failed to parse CST file '%s'\n", filename.c_str());
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}
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}
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gowin_pack(ctx);
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}
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// One DSP macro, in a rough approximation, consists of 5 large operating
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// blocks (pre-adders, multipliers and alu), at almost every input (blocks
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// usually have two of them) you can turn on registers, in addition, there are
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// registers on a dedicated operand shift line between DSP and registers at
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// the outputs. As we see, the number of registers is large, but the DSP has
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// only four inputs for each of the CE, CLK and RESET signals, and here we tell
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// gowin_pack which version of each signal is used by which block.
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// We also indicate to the router which Bel's pin to use.
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void GowinImpl::adjust_dsp_pin_mapping(void)
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{
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for (auto b2c : dsp_bel2cell) {
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BelId bel = b2c.first;
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Loc loc = ctx->getBelLocation(bel);
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CellInfo *ci = b2c.second;
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const auto dsp_data = fast_cell_info.at(ci->flat_index);
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auto set_cell_bel_pin = [&](dict<IdString, int> nets, IdString pin, IdString net_name, const char *fmt,
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const char *fmt_double = nullptr) {
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int i = 0;
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for (auto net_cnt : nets) {
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if (net_cnt.first == net_name) {
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break;
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}
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++i;
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}
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ci->cell_bel_pins.at(pin).clear();
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if (fmt_double == nullptr) {
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ci->cell_bel_pins.at(pin).push_back(ctx->idf(fmt, i));
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} else {
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ci->cell_bel_pins.at(pin).push_back(ctx->idf(fmt_double, i, 0));
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ci->cell_bel_pins.at(pin).push_back(ctx->idf(fmt_double, i, 1));
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}
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ci->setAttr(pin, i);
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};
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if (dsp_data.dsp_reset != nullptr) {
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BelId dsp = ctx->getBelByLocation(Loc(loc.x, loc.y, BelZ::DSP_Z));
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set_cell_bel_pin(dsp_net_cnt.at(dsp).reset, id_RESET, dsp_data.dsp_reset->name, "RESET%d",
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ci->type == id_MULT36X36 ? "RESET%d%d" : nullptr);
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}
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if (dsp_data.dsp_ce != nullptr) {
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BelId dsp = ctx->getBelByLocation(Loc(loc.x, loc.y, gwu.get_dsp_macro(loc.z)));
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set_cell_bel_pin(dsp_net_cnt.at(dsp).ce, id_CE, dsp_data.dsp_ce->name, "CE%d",
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ci->type == id_MULT36X36 ? "CE%d%d" : nullptr);
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}
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if (dsp_data.dsp_clk != nullptr) {
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BelId dsp = ctx->getBelByLocation(Loc(loc.x, loc.y, gwu.get_dsp_macro(loc.z)));
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set_cell_bel_pin(dsp_net_cnt.at(dsp).clk, id_CLK, dsp_data.dsp_clk->name, "CLK%d",
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ci->type == id_MULT36X36 ? "CLK%d%d" : nullptr);
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}
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}
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}
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void GowinImpl::prePlace() { assign_cell_info(); }
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void GowinImpl::postPlace()
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{
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gwu.has_SP32();
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if (ctx->debug) {
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log_info("================== Final Placement ===================\n");
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for (auto &cell : ctx->cells) {
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auto ci = cell.second.get();
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if (ci->bel != BelId()) {
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log_info("%s: %s\n", ctx->nameOfBel(ci->bel), ctx->nameOf(ci));
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} else {
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log_info("unknown: %s\n", ctx->nameOf(ci));
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}
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}
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log_break();
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}
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// adjust cell pin to bel pin mapping for DSP cells (CE, CLK and RESET pins)
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adjust_dsp_pin_mapping();
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}
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void GowinImpl::preRoute() { gowin_route_globals(ctx); }
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void GowinImpl::postRoute()
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{
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std::set<IdString> visited_hclk_users;
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for (auto &cell : ctx->cells) {
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auto ci = cell.second.get();
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if (ci->type.in(id_IOLOGICI, id_IOLOGICO, id_IOLOGIC) ||
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((is_iologici(ci) || is_iologico(ci)) && !ci->type.in(id_ODDR, id_ODDRC, id_IDDR, id_IDDRC))) {
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if (visited_hclk_users.find(ci->name) == visited_hclk_users.end()) {
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// mark FCLK<-HCLK connections
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const NetInfo *h_net = ci->getPort(id_FCLK);
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if (h_net) {
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for (auto &user : h_net->users) {
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if (user.port != id_FCLK) {
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continue;
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}
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user.cell->setAttr(id_IOLOGIC_FCLK, Property("UNKNOWN"));
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visited_hclk_users.insert(user.cell->name);
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// XXX Based on the implementation, perhaps a function
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// is needed to get Pip from a Wire
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PipId up_pip = h_net->wires.at(ctx->getNetinfoSinkWire(h_net, user, 0)).pip;
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IdString up_wire_name = ctx->getWireName(ctx->getPipSrcWire(up_pip))[1];
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if (up_wire_name.in(id_HCLK_OUT0, id_HCLK_OUT1, id_HCLK_OUT2, id_HCLK_OUT3)) {
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user.cell->setAttr(id_IOLOGIC_FCLK, Property(up_wire_name.str(ctx)));
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if (ctx->debug) {
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log_info("set IOLOGIC_FCLK to %s\n", up_wire_name.c_str(ctx));
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}
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}
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if (ctx->debug) {
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log_info("HCLK user cell:%s, port:%s, wire:%s, pip:%s, up wire:%s\n",
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ctx->nameOf(user.cell), user.port.c_str(ctx),
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ctx->nameOfWire(ctx->getNetinfoSinkWire(h_net, user, 0)), ctx->nameOfPip(up_pip),
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ctx->nameOfWire(ctx->getPipSrcWire(up_pip)));
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}
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}
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}
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}
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}
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}
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}
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bool GowinImpl::isBelLocationValid(BelId bel, bool explain_invalid) const
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{
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Loc l = ctx->getBelLocation(bel);
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IdString bel_type = ctx->getBelType(bel);
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if (!ctx->getBoundBelCell(bel)) {
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return true;
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}
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switch (bel_type.hash()) {
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case ID_LUT4: /* fall-through */
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case ID_DFF:
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return slice_valid(l.x, l.y, l.z / 2);
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case ID_ALU:
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return slice_valid(l.x, l.y, l.z - BelZ::ALU0_Z);
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case ID_RAM16SDP4:
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// only slices 4 and 5 are critical for RAM
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return slice_valid(l.x, l.y, l.z - BelZ::RAMW_Z + 5) && slice_valid(l.x, l.y, l.z - BelZ::RAMW_Z + 4);
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case ID_PADD9: /* fall-through */
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case ID_PADD18: /* fall-through */
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case ID_MULT9X9: /* fall-through */
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case ID_MULT18X18: /* fall-through */
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case ID_MULTADDALU18X18: /* fall-through */
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case ID_MULTALU18X18: /* fall-through */
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case ID_MULTALU36X18: /* fall-through */
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case ID_MULT36X36: /* fall-through */
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case ID_ALU54D:
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return dsp_valid(l, bel_type, explain_invalid);
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}
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return true;
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}
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// Bel bucket functions
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IdString GowinImpl::getBelBucketForCellType(IdString cell_type) const
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{
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if (cell_type.in(id_IBUF, id_OBUF)) {
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return id_IOB;
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}
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if (type_is_lut(cell_type)) {
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return id_LUT4;
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}
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if (type_is_dff(cell_type)) {
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return id_DFF;
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}
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if (type_is_ssram(cell_type)) {
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return id_RAM16SDP4;
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}
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if (type_is_iologici(cell_type)) {
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return id_IOLOGICI;
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}
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if (type_is_iologico(cell_type)) {
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return id_IOLOGICO;
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}
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if (type_is_bsram(cell_type)) {
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return id_BSRAM;
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}
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if (cell_type == id_GOWIN_GND) {
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return id_GND;
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}
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if (cell_type == id_GOWIN_VCC) {
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return id_VCC;
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}
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return cell_type;
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}
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bool GowinImpl::isValidBelForCellType(IdString cell_type, BelId bel) const
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{
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if (cell_type == id_DUMMY_CELL) {
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return true;
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}
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IdString bel_type = ctx->getBelType(bel);
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if (bel_type == id_IOB) {
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return cell_type.in(id_IBUF, id_OBUF);
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}
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if (bel_type == id_LUT4) {
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return type_is_lut(cell_type);
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}
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if (bel_type == id_DFF) {
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return type_is_dff(cell_type);
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}
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if (bel_type == id_RAM16SDP4) {
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return type_is_ssram(cell_type);
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}
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if (bel_type == id_IOLOGICI) {
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return type_is_iologici(cell_type);
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}
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if (bel_type == id_IOLOGICO) {
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return type_is_iologico(cell_type);
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}
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if (bel_type == id_BSRAM) {
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return type_is_bsram(cell_type);
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}
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if (bel_type == id_GND) {
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return cell_type == id_GOWIN_GND;
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}
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if (bel_type == id_VCC) {
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return cell_type == id_GOWIN_VCC;
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}
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return (bel_type == cell_type);
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}
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void GowinImpl::assign_cell_info()
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{
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fast_cell_info.resize(ctx->cells.size());
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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auto &fc = fast_cell_info.at(ci->flat_index);
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if (is_lut(ci)) {
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fc.lut_f = ci->getPort(id_F);
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continue;
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}
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if (is_dff(ci)) {
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fc.ff_d = ci->getPort(id_D);
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fc.ff_clk = ci->getPort(id_CLK);
|
|
fc.ff_ce = ci->getPort(id_CE);
|
|
for (IdString port : {id_SET, id_RESET, id_PRESET, id_CLEAR}) {
|
|
fc.ff_lsr = ci->getPort(port);
|
|
if (fc.ff_lsr != nullptr) {
|
|
break;
|
|
}
|
|
}
|
|
continue;
|
|
}
|
|
if (is_alu(ci)) {
|
|
fc.alu_sum = ci->getPort(id_SUM);
|
|
continue;
|
|
}
|
|
auto get_net = [&](IdString port_id) {
|
|
NetInfo *ni = ci->getPort(port_id);
|
|
if (ni != nullptr && ni->driver.cell == nullptr) {
|
|
ni = nullptr;
|
|
}
|
|
return ni;
|
|
};
|
|
if (is_dsp(ci)) {
|
|
fc.dsp_reset = get_net(id_RESET);
|
|
fc.dsp_clk = get_net(id_CLK);
|
|
fc.dsp_ce = get_net(id_CE);
|
|
fc.dsp_asign = get_net(id_ASIGN);
|
|
fc.dsp_bsign = get_net(id_BSIGN);
|
|
fc.dsp_asel = get_net(id_ASEL);
|
|
fc.dsp_bsel = get_net(id_BSEL);
|
|
fc.dsp_soa_reg = ci->params.count(id_SOA_REG) && ci->params.at(id_SOA_REG).as_int64() == 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
// DFFs must be same type or compatible
|
|
inline bool incompatible_ffs(const CellInfo *ff, const CellInfo *adj_ff)
|
|
{
|
|
return ff->type != adj_ff->type &&
|
|
((ff->type == id_DFFS && adj_ff->type != id_DFFR) || (ff->type == id_DFFR && adj_ff->type != id_DFFS) ||
|
|
(ff->type == id_DFFSE && adj_ff->type != id_DFFRE) || (ff->type == id_DFFRE && adj_ff->type != id_DFFSE) ||
|
|
(ff->type == id_DFFP && adj_ff->type != id_DFFC) || (ff->type == id_DFFC && adj_ff->type != id_DFFP) ||
|
|
(ff->type == id_DFFPE && adj_ff->type != id_DFFCE) || (ff->type == id_DFFCE && adj_ff->type != id_DFFPE) ||
|
|
(ff->type == id_DFFNS && adj_ff->type != id_DFFNR) || (ff->type == id_DFFNR && adj_ff->type != id_DFFNS) ||
|
|
(ff->type == id_DFFNSE && adj_ff->type != id_DFFNRE) ||
|
|
(ff->type == id_DFFNRE && adj_ff->type != id_DFFNSE) ||
|
|
(ff->type == id_DFFNP && adj_ff->type != id_DFFNC) || (ff->type == id_DFFNC && adj_ff->type != id_DFFNP) ||
|
|
(ff->type == id_DFFNPE && adj_ff->type != id_DFFNCE) ||
|
|
(ff->type == id_DFFNCE && adj_ff->type != id_DFFNPE));
|
|
}
|
|
|
|
// placement validation
|
|
bool GowinImpl::dsp_valid(Loc l, IdString bel_type, bool explain_invalid) const
|
|
{
|
|
const CellInfo *dsp = ctx->getBoundBelCell(ctx->getBelByLocation(l));
|
|
const auto &dsp_data = fast_cell_info.at(dsp->flat_index);
|
|
// check for shift out register - there is only one for macro
|
|
if (dsp_data.dsp_soa_reg) {
|
|
if (l.z == BelZ::MULT18X18_0_1_Z || l.z == BelZ::MULT18X18_1_1_Z || l.z == BelZ::MULT9X9_0_0_Z ||
|
|
l.z == BelZ::MULT9X9_0_1_Z || l.z == BelZ::MULT9X9_1_0_Z || l.z == BelZ::MULT9X9_1_1_Z) {
|
|
if (explain_invalid) {
|
|
log_nonfatal_error(
|
|
"It is not possible to place the DSP so that the SOA register is on the macro boundary.\n");
|
|
}
|
|
return false;
|
|
}
|
|
}
|
|
|
|
if (bel_type.in(id_MULT9X9, id_PADD9)) {
|
|
int pair_z = gwu.get_dsp_paired_9(l.z);
|
|
const CellInfo *adj_dsp9 = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(l.x, l.y, pair_z)));
|
|
if (adj_dsp9 != nullptr) {
|
|
const auto &adj_dsp9_data = fast_cell_info.at(adj_dsp9->flat_index);
|
|
if ((dsp_data.dsp_asign != adj_dsp9_data.dsp_asign) || (dsp_data.dsp_bsign != adj_dsp9_data.dsp_bsign) ||
|
|
(dsp_data.dsp_asel != adj_dsp9_data.dsp_asel) || (dsp_data.dsp_bsel != adj_dsp9_data.dsp_bsel) ||
|
|
(dsp_data.dsp_reset != adj_dsp9_data.dsp_reset) || (dsp_data.dsp_ce != adj_dsp9_data.dsp_ce) ||
|
|
(dsp_data.dsp_clk != adj_dsp9_data.dsp_clk)) {
|
|
if (explain_invalid) {
|
|
log_nonfatal_error("For 9bit primitives the control signals must be same.\n");
|
|
}
|
|
return false;
|
|
}
|
|
}
|
|
}
|
|
// check for control nets "overflow"
|
|
BelId dsp_bel = ctx->getBelByLocation(Loc(l.x, l.y, BelZ::DSP_Z));
|
|
if (dsp_net_cnt.at(dsp_bel).reset.size() > 4) {
|
|
if (explain_invalid) {
|
|
log_nonfatal_error("More than 4 different networks for RESET signals in one DSP are not allowed.\n");
|
|
}
|
|
return false;
|
|
}
|
|
BelId dsp_macro_bel = ctx->getBelByLocation(Loc(l.x, l.y, gwu.get_dsp_macro(l.z)));
|
|
if (dsp_net_cnt.count(dsp_macro_bel)) {
|
|
if (dsp_net_cnt.at(dsp_macro_bel).ce.size() > 4 || dsp_net_cnt.at(dsp_macro_bel).clk.size() > 4) {
|
|
if (explain_invalid) {
|
|
log_nonfatal_error(
|
|
"More than 4 different networks for CE or CLK signals in one DSP macro are not allowed.\n");
|
|
}
|
|
return false;
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool GowinImpl::slice_valid(int x, int y, int z) const
|
|
{
|
|
const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
|
|
const bool lut_in_4_5 = lut && (z == 4 || z == 5);
|
|
const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
|
|
// There are only 6 ALUs
|
|
const CellInfo *alu = (z < 6) ? ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z + BelZ::ALU0_Z))) : nullptr;
|
|
const CellInfo *ramw =
|
|
(z == 4 || z == 5) ? ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, BelZ::RAMW_Z))) : nullptr;
|
|
|
|
if (alu && lut) {
|
|
return false;
|
|
}
|
|
|
|
if (ramw) {
|
|
if (alu || ff || lut_in_4_5) {
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
// check for ALU/LUT in the adjacent cell
|
|
int adj_lut_z = (1 - (z & 1) * 2 + z) * 2;
|
|
int adj_alu_z = adj_lut_z / 2 + BelZ::ALU0_Z;
|
|
const CellInfo *adj_lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_lut_z)));
|
|
const CellInfo *adj_ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_lut_z + 1)));
|
|
const CellInfo *adj_alu = adj_alu_z < (6 + BelZ::ALU0_Z)
|
|
? ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_alu_z)))
|
|
: nullptr;
|
|
|
|
if ((alu && (adj_lut || (adj_ff && !adj_alu))) || ((lut || (ff && !alu)) && adj_alu)) {
|
|
return false;
|
|
}
|
|
|
|
// if there is DFF it must be connected to this LUT or ALU
|
|
if (ff) {
|
|
const auto &ff_data = fast_cell_info.at(ff->flat_index);
|
|
if (lut) {
|
|
const auto &lut_data = fast_cell_info.at(lut->flat_index);
|
|
if (ff_data.ff_d != lut_data.lut_f) {
|
|
return false;
|
|
}
|
|
}
|
|
if (alu) {
|
|
const auto &alu_data = fast_cell_info.at(alu->flat_index);
|
|
if (ff_data.ff_d != alu_data.alu_sum) {
|
|
return false;
|
|
}
|
|
}
|
|
if (adj_ff) {
|
|
if (incompatible_ffs(ff, adj_ff)) {
|
|
return false;
|
|
}
|
|
|
|
// CE, LSR and CLK must match
|
|
const auto &adj_ff_data = fast_cell_info.at(adj_ff->flat_index);
|
|
if (adj_ff_data.ff_lsr != ff_data.ff_lsr) {
|
|
return false;
|
|
}
|
|
if (adj_ff_data.ff_clk != ff_data.ff_clk) {
|
|
return false;
|
|
}
|
|
if (adj_ff_data.ff_ce != ff_data.ff_ce) {
|
|
return false;
|
|
}
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
// Cluster
|
|
bool GowinImpl::getClusterPlacement(ClusterId cluster, BelId root_bel,
|
|
std::vector<std::pair<CellInfo *, BelId>> &placement) const
|
|
{
|
|
CellInfo *root_ci = getClusterRootCell(cluster);
|
|
if (!root_ci->type.in(id_PADD9, id_MULT9X9, id_PADD18, id_MULT18X18, id_MULTALU18X18, id_MULTALU36X18,
|
|
id_MULTADDALU18X18, id_ALU54D)) {
|
|
return HimbaechelAPI::getClusterPlacement(cluster, root_bel, placement);
|
|
}
|
|
|
|
NPNR_ASSERT(root_bel != BelId());
|
|
if (!isValidBelForCellType(root_ci->type, root_bel)) {
|
|
return false;
|
|
}
|
|
|
|
IdString bel_type = ctx->getBelType(root_bel);
|
|
// non-chain DSP
|
|
if (root_ci->constr_children.size() == 1 && bel_type.in(id_PADD9, id_MULT9X9)) {
|
|
return HimbaechelAPI::getClusterPlacement(cluster, root_bel, placement);
|
|
}
|
|
|
|
placement.clear();
|
|
Loc root_loc = ctx->getBelLocation(root_bel);
|
|
placement.emplace_back(root_ci, root_bel);
|
|
|
|
Loc mult_loc = root_loc;
|
|
for (auto child : root_ci->constr_children) {
|
|
Loc child_loc;
|
|
child_loc.y = root_loc.y;
|
|
if (child->type == id_DUMMY_CELL) {
|
|
child_loc.x = mult_loc.x + child->constr_x;
|
|
child_loc.z = mult_loc.z + child->constr_z;
|
|
} else {
|
|
child_loc = gwu.get_dsp_next_in_chain(mult_loc, child->type);
|
|
mult_loc = child_loc;
|
|
}
|
|
|
|
BelId child_bel = ctx->getBelByLocation(child_loc);
|
|
if (child_bel == BelId() || !isValidBelForCellType(child->type, child_bel))
|
|
return false;
|
|
placement.emplace_back(child, child_bel);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
void GowinImpl::notifyBelChange(BelId bel, CellInfo *cell)
|
|
{
|
|
if (cell != nullptr && !is_dsp(cell)) {
|
|
return;
|
|
}
|
|
if (cell == nullptr && dsp_bel2cell.count(bel) == 0) {
|
|
return;
|
|
}
|
|
|
|
// trace DSP control networks
|
|
IdString cell_type = id_DUMMY_CELL;
|
|
if (cell != nullptr) {
|
|
cell_type = cell->type;
|
|
}
|
|
Loc loc = ctx->getBelLocation(bel);
|
|
Loc l = loc;
|
|
l.z = gwu.get_dsp(loc.z);
|
|
BelId dsp = ctx->getBelByLocation(l);
|
|
l.z = gwu.get_dsp_macro(loc.z);
|
|
BelId dsp_macro = ctx->getBelByLocation(l);
|
|
|
|
if (cell) {
|
|
const auto &dsp_cell_data = fast_cell_info.at(cell->flat_index);
|
|
if (dsp_cell_data.dsp_reset != nullptr) {
|
|
dsp_net_cnt[dsp].reset[dsp_cell_data.dsp_reset->name]++;
|
|
}
|
|
if (dsp_cell_data.dsp_ce != nullptr) {
|
|
dsp_net_cnt[dsp_macro].ce[dsp_cell_data.dsp_ce->name]++;
|
|
}
|
|
if (dsp_cell_data.dsp_clk != nullptr) {
|
|
dsp_net_cnt[dsp_macro].clk[dsp_cell_data.dsp_clk->name]++;
|
|
}
|
|
dsp_bel2cell[bel] = cell;
|
|
} else {
|
|
const auto &dsp_cell_data = fast_cell_info.at(dsp_bel2cell.at(bel)->flat_index);
|
|
if (dsp_cell_data.dsp_reset != nullptr) {
|
|
dsp_net_cnt.at(dsp).reset.at(dsp_cell_data.dsp_reset->name)--;
|
|
}
|
|
if (dsp_cell_data.dsp_ce != nullptr) {
|
|
dsp_net_cnt.at(dsp_macro).ce.at(dsp_cell_data.dsp_ce->name)--;
|
|
}
|
|
if (dsp_cell_data.dsp_clk != nullptr) {
|
|
dsp_net_cnt.at(dsp_macro).clk.at(dsp_cell_data.dsp_clk->name)--;
|
|
}
|
|
dsp_bel2cell.erase(bel);
|
|
}
|
|
}
|
|
|
|
} // namespace
|
|
|
|
NEXTPNR_NAMESPACE_END
|